Process for effectively controlling air bubble producing in forming process of fluorine-containing silex glass interlayer medium layer

Abstract

According to a method of the invention that air bubble is effectively controlled to be produced in the formation of an inter-layer medium layer of fluorine-contained silicon glass, a final inter-layer medium layer (I) with three-layer structure is formed and an HDP-SRO layer (9) is formed on a formed PE-Oxide medium layer of a capacitor before a final protection layer (II) with three-layer structure is formed, which causes the existing final protection layer (II) formed with three-layer structure to become a final protection layer (III) with fourth-layer structure by adding the HDP-SRO layer (9), thus preventing fluorine ions from escaping from the inter-layer medium layer of the fluorine-contained silicon glass and improving the product percent of pass.

Description

technical field [0001] The invention generally relates to a manufacturing method of a semiconductor device, in particular to a method for effectively controlling bubbles generated during the formation of a fluorine-containing silicon glass interlayer dielectric layer. Background technique [0002] As is well known to those skilled in the art, a semiconductor device has a multi-layer film structure, including multiple metal layers and multiple dielectric layers and protective layers. The metal layer therein constitutes the metal connection lines in the semiconductor device. In order to prevent short circuits between adjacent metal layers, an interlayer dielectric layer is placed between adjacent metal layers. The interlayer dielectric layer is usually formed by depositing a layer of fluorine-containing silicate glass by high-density plasma. [0003] However, if the interlayer dielectric layer containing fluorine-silicate glass is formed by high-density plasma deposition, af...

AI Technical Summary

Problems solved by technology

Bubbles in the interlayer dielectric layer of fluorine-containing silicate glass cause damage to the performance of the interlayer dielectric layer, and the interlayer dielectric layer cannot completely prevent the short circuit of the adjacent metal layer, resulting in a decrease in the performance of the semiconductor device or even damage

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