Multipath accessible semiconductor memory device

Abstract

A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory.; The control unit also controls a connection path between the shared memory area and one of the first and second processors. The processors share the flash memory and a multiprocessor system is provided that has a compact size, thereby substantially reducing the cost of memory utilized within the multiprocessor system.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor memory devices. More specifically, embodiments of the present invention relate to a multipath accessible semiconductor memory device applicable between multiple processors. Background technique [0002] Generally, a semiconductor memory device having multiple access ports is called a multi-port memory. A memory device with two access ports is called a dual-port memory. A typical dual-port memory is used as video memory for image processing, having a RAM (Random Access Memory) port accessible in random order and a SAM (Sequential Access Memory) port accessible only in sequential order. A dynamic random access memory (DRAM) is configured to read from or write to a shared memory area in a memory cell array through a plurality of access ports. A DRAM without a SAM port is referred to herein as a multi-path accessible semiconductor memory device to distinguish it from a multi-port memory device...

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Also, this interfacing compromises transfer speed and increases device pin count

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