Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for flash technology high-voltage bar oxygen and tunnel-penetration oxidation layer

A technology of tunneling oxide layer and gate oxide layer, which is applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of reduced erasing ability, failure, and reduced electric field strength, so as to increase the number of erasing and writing. Effect

Active Publication Date: 2008-04-30
SHANGHAI HUAHONG GRACE SEMICON MFG CORP +1
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the number of erasing and writing increases, the charge traps in the tunnel oxide layer will increase accordingly, so that more and more electrons are trapped in the charge traps during the tunneling process, so that the electric field between the control gate and the floating gate The strength is reduced due to the shielding of the trapped charges, the erasability is continuously reduced, and eventually it fails because it cannot be erased

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for flash technology high-voltage bar oxygen and tunnel-penetration oxidation layer
  • Method for flash technology high-voltage bar oxygen and tunnel-penetration oxidation layer
  • Method for flash technology high-voltage bar oxygen and tunnel-penetration oxidation layer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0017] Reducing the thickness of the tunnel oxide layer, under the same working conditions, not only directly enhances the electric field strength during erasing, but also reduces the number of traps in the oxide layer, which is conducive to improving the erasing ability of the memory cell, thereby increasing its erasing and writing times . When the tunnel oxide thickness is reduced to 160 , its erase and write times can reach 200,000 times.

[0018] However, the thickness of the high-voltage oxide layer must meet the withstand voltage requirements of the high-voltage transistor. Since flash memory uses a voltage as high as 12-14V, the total thickness of the high-voltage gate oxide layer needs to be greater than 180 In order to ensure its normal operation and reliability requirements. In the current process in which the high-voltage gate oxide and the tunnel oxide layer are formed simultaneously, it is difficult to further reduce the thickness of the tunnel oxide layer. ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for forming a high-voltage gate oxide and a tunneling oxide layer in a flash memory process. Firstly, the floating gate oxide layer after floating gate etching is retained, and its thickness is 50-70; secondly, the floating gate oxide layer is The layer is etched by a wet method, and its thickness is kept at 20-30; after that, a tunnel oxide layer and a high-voltage gate oxide layer are simultaneously formed by using a high-temperature and reduced-pressure chemical vapor deposition process; finally, the thickness of the tunnel oxide layer formed is 160-180, the high-voltage gate oxide layer is formed with a thickness of 180-210. By reducing the thickness of the tunnel oxide layer, the present invention not only enhances the electric field intensity during erasing, but also reduces the number of traps in the oxide layer correspondingly, thereby improving the erasing ability of the memory unit.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit process method, in particular to a method for forming a high-voltage gate oxide and a tunnel oxide layer in a flash memory process. Background technique [0002] As a main non-volatile memory, flash memory is widely used in smart cards, microcontrollers and other fields. Compared with EEPORM, another non-volatile memory, flash memory has obvious advantages in area; but at the same time, the reliability of flash memory, especially the erasable number of times, is worse than EEPROM, so it is used in bank cards, ID cards, etc. Product has not yet been used. [0003] SST flash memory is a type of flash memory invented by Bing Yeh in 1990 (US Patent No. 5029130), and the structure of its storage unit is as follows figure 1 shown. Among them, polycrystalline 1 is a floating gate, and the following is 80~90 Thick floating gate oxide layer. A part of the polycrystalline 2 covers the floating gat...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/336H01L21/28H01L21/31H01L21/8247
Inventor 杨斌李铭龚新军杨鹏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products