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Structure and method for controlling the behavior of dislocations in strained semiconductor layers

A semiconductor and control bit technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of inability to obtain and control the formation of S/D

Inactive Publication Date: 2007-09-19
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Such very thin layers are not available in conventional CMOS fabrication
However, due to the enhanced dopant diffusion of As or P in SiGe, S / D formation is not well controlled after ion implantation and S / D activation annealing

Method used

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  • Structure and method for controlling the behavior of dislocations in strained semiconductor layers
  • Structure and method for controlling the behavior of dislocations in strained semiconductor layers
  • Structure and method for controlling the behavior of dislocations in strained semiconductor layers

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Embodiment Construction

[0017] Figure 1 shows a cross-sectional view of a MOSFET 10 formed on a strained semiconductor layer 12, which is Si or contains Si. Strained layer 12 is formed on SiGe layer 16 , which in turn is formed on substrate 20 . The strained layer 12 may be formed by epitaxial deposition on the SiGe layer 16 . SiGe layer 16 may be formed by epitaxial deposition on substrate 20, which may be single crystal. The amount of germanium in layer 16 increases with the thickness of the layer and then relaxes to form a lattice spacing greater than that of the future lower surface of layer 12 , resulting in a global bidirectional strain in layer 12 . Thus, layer 16 may be graded SiGe, up to upper surface 17 of layer 16 . Layer 12 may be of constant Si or SiGe composition.

[0018] Alternatively, instead of the SiGe graded layer 16, the layer 16 may be silicon germanium on insulator (SGOI) as shown in FIG. 2 .

[0019] In FIGS. 1-5 , MOSFET 10 has source 22 , drain 23 and gate 24 . There ar...

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Abstract

A structure and method for controlling the behavior of dislocations in strained semiconductor layers is described incorporating a graded alloy region to provide a strain gradient to change the slope or curvature of a dislocation propagating upwards or gliding in the semiconductor layer in the proximity of the source and drain of a MOSFET. The upper surface of the strained semiconductor layer may be roughened and / or contain a dielectric layer or silicide which may be patterned to trap the upper end of dislocations in selected surface areas. The invention solves the problem of dislocation segments passing through both the source and drain of a MOSFET creating leakage currents or shorts therebetween.

Description

technical field [0001] The present invention relates to strained semiconductor layers for forming integrated circuit chips, and more particularly to controlling the behavior of dislocations in strained semiconductor layers. Background technique [0002] The formation of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the Si layer under tensile strain has allowed the continued development of high-performance / low-power CMOS integrated circuits. The increased carrier mobility in strained Si compared to that in unstrained Si allows increasing the on-state transistor current without reducing the physical size of the device; where reducing the physical size of the device has become increasingly more difficult. For the application of strained Si, the two main methods used to generate strain in the transistor channel region are: 1) growing a thin Si layer on a relaxed SiGe alloy layer (global strain) and 2) using an integrated circuit (IC) Process-level techniques ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/02H01L29/78H01L21/20H01L21/336
CPCH01L29/7843H01L29/78H01L21/823807H01L29/1054
Inventor S·W·比德尔D·K·萨达那A·雷茨尼采克J·P·德索萨K·W·施瓦茨
Owner INT BUSINESS MASCH CORP
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