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Chip packaging structure and method of producing the same

A technology of chip packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of adhesive overflow contaminating solder pads and contaminating circuits, etc.

Inactive Publication Date: 2009-08-26
POWERTECH TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to solve the situation that the bonding pads on the chips are polluted by the overflow of the die-bonding glue when sticking the chips, one of the objects of the present invention is to provide a chip packaging structure and a manufacturing method thereof, which uses a stopper element to be arranged on the periphery of the substrate opening to stop the sticking. When the crystal glue is pressed, it overflows toward the opening of the substrate and pollutes the pads on the chip, or overflows toward the outside of the substrate and contaminates other circuits on the substrate.

Method used

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  • Chip packaging structure and method of producing the same
  • Chip packaging structure and method of producing the same
  • Chip packaging structure and method of producing the same

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Embodiment Construction

[0034] The detailed description is as follows, and the preferred embodiment is only for illustration and not intended to limit the present invention.

[0035] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G-1 and Figure 2G-2 Structural cross-sectional view of each step of the manufacturing method of the chip packaging structure according to an embodiment of the present invention. First, please refer to Figure 2A , provide a substrate 10, which is made of metal, glass, ceramics or polymer material, and has at least one opening 12 through the substrate 10, wherein the substrate 10 can be formed by using a suitable method to penetrate the substrate 10, or it can have at least one The commercialized structure of the opening 12.

[0036] Next, refer to Figure 2B , forming a blocking element 20 on the periphery of the opening 12 on the upper surface 11 of the substrate 10 . In one embodiment, the stop member 20 is formed by one of...

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Abstract

This invention relates to a packaging structure of chips and a manufacturing method including: providing a base board with at least one open-end through it, forming a block element surrounding the open-end of the board, forming an adhering element around the block element, setting a chip on the board and covering the open-end and fixing it with the adhering element on the board, in which, the active surface of the chip is facing to the open-end and part of which exposes it, utilizing a conduction connection element to pass through the open and connect with the active surface of the chip and the bottom surface of the base board electrically and forming a packaging colloid to wrap the element, in which, when the block element is set around the open to resist against adhering the chip, the overflow of the adhering element pollutes the conducting connection points on the active surface of the chip and limits height of the adhering element to reduce the probability of harming the active surface of chips by dust (such as EMC fillers).

Description

technical field [0001] The invention relates to a chip packaging structure and a manufacturing method thereof, in particular to a window-opening type chip packaging structure and a manufacturing method thereof for preventing adhesive overflow. Background technique [0002] With the rapid development of the semiconductor industry, the design of electronic products in IC (integrated) components is developing towards the demand for multi-pin count and multi-function, and the appearance of components is also developing towards the trend of light, thin, short and small. Therefore, the packaging process also faces many challenges, such as the increasingly complex design of the lead frame, the selection of packaging materials, warping of thin packages, heat dissipation and structural strength, etc. These are all problems encountered by the current packaging industry. [0003] Known general windowed ball grid array package structure, such as Figure 1A As shown, a circuit substrate ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/12H01L23/31H01L21/50
CPCH01L2224/92147H01L2224/4824H01L2224/73215H01L2224/48091H01L2224/83192H01L2224/32225H01L2924/0002H01L2924/15311H01L2224/27013H01L2924/00014H01L2924/00
Inventor 陈锦弟
Owner POWERTECH TECHNOLOGY
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