Erasing method of single-gate non-volatile memory

Abstract

The invention relates to a method for erasing single-gate non-volatile memory. Wherein, it has single flow gate polar structure; when it erases, it functions voltage on door polar to generate reverse layer. The invention can reduce erasing voltage and improve erasing speed, and it can avoid over erase.

Description

technical field [0001] The present invention relates to a non-volatile memory (Non-Volatile Memory), in particular to a method for erasing a single-gate non-volatile memory that can be erased at low voltage (lower than 10V). Background technique [0002] Press, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) preparation technology has become a common manufacturing method of application specific integrated circuit (ASIC). Today, with the development of computer information products, Electronically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read Only Memory, EEPROM) has the function of electrically writing and erasing data, and after the power is turned off Data will not disappear, so it is widely used in electronic products. [0003] Non-volatile memory is programmable by storing charge to change the gate voltage of the memory's transistors, or not storing charge to leave the gate voltage of the original...

AI Technical Summary

Problems solved by technology

Therefore, in the structure of the known non-volatile memory, in addition to the gate layer of the transistor, an additional conductive layer is required to store charges, and the formation of a double-gate (double-layer) structure is more expensive than the general one. CMOS preparation requires more steps such as film deposition, etching, exposure and development, which increases cost, complicates preparation, reduces component yield, and increases man-hours, especially when used in embedded (Embedded) EEPROM products.

[0004] In the known erasing method for EEPROM components, the stored charge is moved from the floating gate to the transistor under the tunneling effect of the Fowler-Nordheim (Fowler-Nordheim) tunneling (referred to as F-N tunneling) technology. Removed, the voltage often needs to be greater than 10V, and because the structure of the single-gate EEMPROM memory is transistor substrate-floating gate-capacitor substrate, the stored charge can be released to any direction according to the direction of the electric field; resulting in a single-gate The over-erasing problem of extremely EEPROM components becomes more serious

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