Accuracy improvements in optical metrology

Abstract

Methods, metrology modules and target designs are provided, which improve the accuracy of metrology measurements. Methods provide flexible handling of multiple measurement recipes and setups and enable relating them to landscape features that indicate their relation to resonance regions and to flat regions. Clustering of recipes, self-consistency tests, common processing of aggregated measurements, noise reduction, cluster analysis, detailed analysis of the landscape and targets with skewed cells are employed separately or in combination to provide cumulative improvements of measurement accuracy.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Patent Application No. 62 / 299,535 filed on Feb. 24, 2016, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION1. Technical Field[0002]The present invention relates to the field of metrology, and more particularly, to techniques that achieve better accuracy in optical metrology,2. Discussion of Related Art[0003]Various optical metrology technologies require that the process variations which cause asymmetry in the metrology signal be much smaller than some threshold, so that the part of the asymmetry signal is much smaller than the signal asymmetry caused by the overlay. In reality, however, such process variations may be quite large (especially in the research and development phase of chip development) and they may induce sizeable errors in the overlay reported by the metrology; errors that may reach the nanometer regime, thereby consuming a significan...

AI Technical Summary

Benefits of technology

The present invention provides a method for improving the accuracy of measurement in a metrology pupil image by modifying a pixel value based on the average of neighboring pixel values to reduce random noise. The invention also provides combinations of methods that provide cumulative improvements in measurement accuracy.

Problems solved by technology

In reality, however, such process variations may be quite large (especially in the research and development phase of chip development) and they may induce sizeable errors in the overlay reported by the metrology; errors that may reach the nanometer regime, thereby consuming a significant part of the overlay metrology' budget.

However, prior art methodologies do not estimate reliably the inaccuracy of the metrology in train and cannot do so at all in run time using traditional recipe optimization (e.g., using CDSEM—critical dimensions scanning electron microscopy to calibrate the measurement); and the presence of process variations that are symmetric (for example, a change in a certain layer's thickness of an overlay mark), may make the recipe optimization obsolete since different recipes may perform differently during research and development, in train and in runtime.

Such a problem may also take place across the wafer, as different recipes may perform differently over different regions of the wafer.

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