Rapid I/O Traffic System

Abstract

High speed networking systems such as PCI-Express and Serial Rapid I / O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a divisional of U.S. patent application Ser. No. 11 / 383,330, filed May 15, 2006, which claims priority from 60 / 680,592, filed May 13, 2005 AND 60 / 681,427 filed May 16, 2005, all herein incorporated by reference.TECHNICAL FIELD OF THE INVENTION[0002]The technical field of this invention is input / output technology.BACKGROUND OF THE INVENTION[0003]During applications code development, the development team traverses a repetitive development cycle shown below hundreds if not thousands of times:[0004]1. Building code—compile and link a version of applications code[0005]2. Loading code—loading the code into real hardware system or a software model[0006]3. Debugging / Profiling code—chasing correctness or performance problems[0007]4. Making changes—making source code edits, or changing the linker directives[0008]The load and change portions of this cycle are generally viewed as non-productive time, as one is either waiting for c...

AI Technical Summary

Benefits of technology

[0024]New high speed networking system such as PCI-Express and Serial Rapid I / O are based on the exchange of packets across switched networks of high speed serial links. Queuing all received packets in a single FIFO queue will cause interactions between transaction types. Indirection may be used to create the effect of multiple independent FIFOs from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types and preventing Head-Of-Line blocking between them.

Problems solved by technology

The load and change portions of this cycle are generally viewed as non-productive time, as one is either waiting for code to download from the host to the target system or looking through files that need changes and making changes with a text editor.

This inaccuracy results in a loss of confidence about the capabilities of the device and leads to fictitious performance de-rating factors between cache and flat memory performance.

While some of the discrepancy between simulated and actual performance is due to inadequate modeling of the cache, there still exists a fundamental problem in modeling system related interactions such as interrupts or DMA accurately.

The period over which the simulator for a given target matures is unfortunately the same time that a developer is attempting to get to market.

The absence of visibility leaves software developers with little else but to speculate about the probable reasons for loss of performance.

In addition on the C6x Digital Signal Processor (DSP) data memory corruption can also result in program memory corruption causing the CPU execution to crash, as program and data share a unified memory.

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