Methods of forming vertical transistors

Abstract

A vertical transistor forming method includes forming a first pillar above a first source / drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming a front gate and back gate over opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material to substantially fill the first recess, forming the back gate, and only partially fill the second recess, forming the front gate, forming a second source / drain elevationally above the first source / drain, and providing a transistor channel in the first pillar. The channel is operationally associated with the first and second sources / drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.

Description

TECHNICAL FIELD[0001]The invention pertains to methods of forming vertical transistors, including those configured to exhibit a floating body effect.BACKGROUND OF THE INVENTION[0002]Along with continuing efforts to improve data access speed and decrease power consumption in dynamic random access memory (DRAM), capacitorless memory technologies emerged as an area of interest. Corresponding desires to scale down memory devices created doubt regarding whether the standard one transistor / one capacitor cell design may provide the desired progress. Capacitorless memory relies upon the floating body effect of field effect transistors instead of a storage capacitor to provide a memory cell. Kuo, et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications,” IEEE Int'l Electron Devices Meeting (IEDM) Tech. Dig., 2002, pages 843-846 as well as U.S. Pat. No. 6,632,723 issued Oct. 14, 2003 to Watanabe et al. (hereinafter, Watanabe) describe use of capacitorless memory cel...

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Problems solved by technology

Corresponding desires to scale down memory devices created doubt regarding whether the standard one transistor / one capacitor cell design may provide the desired progress.

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