Driver for multi-voltage island/core architecture

Abstract

A system and method for providing a driver for a multi-voltage island / core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island / core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.

Description

BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The invention relates generally to multi-voltage island / core architectures, and more particularly, to a driver for a multi-voltage island / core architecture. [0003] 2. Background Art [0004] As complementary metal oxide semiconductor (CMOS) technologies are scaled, total chip power dissipation is becoming high and is limiting the performance of an integrated circuit chip. Simultaneously, static (leakage) power dissipation is becoming a significant component of total chip power dissipation. A multi-voltage island / core architecture is a solution to the power dissipations. A multi-voltage island / core architecture is designed to independently adjust the voltage supply (Vdd) of each function block in an integrated circuit chip so that the total and the static power dissipation is minimized for each function block while still meeting the chip performance requirements. Each function block with a voltage supply may be referred to as...

AI Technical Summary

Benefits of technology

[0007] A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-

Problems solved by technology

As complementary metal oxide semiconductor (CMOS) technologies are scaled, total chip power dissipation is becoming high and is limiting the performance of an integrated circuit chip.

Simultaneously, static (leakage) power dissipation is becoming a significant component of total chip power dissipation.

One problem is how to build a driver between two voltage islands / cores that have different Vdd.

However, a CMOS inverter also has the problem of leakage, i.e., subthreshold leakage current.

Raising threshold voltage of a CMOS inverter may reduce leakage and may increase noise margin, but may also result in serious loss in performance, for example, prolonged rise time.

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