Structure and method for thin single or multichip semiconductor QFN packages

Abstract

A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second surfaces (111b) are coplanar (130) with the passive chip surface (101b). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound (150) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar (130) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 μm. Reflow metals may be on the passive chip surface and the second segment surfaces.

Description

FIELD OF THE INVENTION [0001] The present invention is related in general to the field of semiconductor devices and processes, and more specifically to structure and method of thin single or multichip semiconductor QFN devices. DESCRIPTION OF THE RELATED ART [0002] Leadframes for semiconductor devices provide a stable support pad for firmly positioning the semiconductor chip, usually an integrated circuit (IC) chip, within a package. It has been common practice to manufacture single piece leadframes from thin (about 120 to 250 μm) sheets of metal. For electrical and thermal reasons, copper has been the favorite starting material; however, the copper price has recently been climbing sharply. [0003] In addition to the chip pad, the leadframe offers a plurality of conductive segments to bring various electrical conductors into close proximity of the chip. The remaining gaps between the segments and the contact pads on the chip surface are bridged by connectors, typically thin metal wir...

AI Technical Summary

Benefits of technology

[0008] Applicant recognizes the need for a fresh concept of achieving low-cost device fabrication using leadframe structures tailor-made for thin semiconductor packages and high reliability devices. The low-cost leadframes are to offer a combination of adhesion to molding compounds, bondability for connecting wires, solderablity of the exposed leadframe segments, and short paths for thermal power dissipation.

[0009] There are technical advantages, when the leadframe and its method of fabrication are flexible and low cost enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations, and achieve improvements toward the goals of improved process yields, high manufacturing throughput, and device reliability. Of special interest are solutions, which can be applied to single and multi-chip products. There are further technical advantages, when these innovations are accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.

[0013] It is an advantage that the grinding technique does not require specific powders, rinsing or cleaning, and the grinding rate is equal for the involved metals, polymers, and semiconductors. The employed technique is easy to control, an advantage for fabricating ultra-thin packages.

Problems solved by technology

For electrical and thermal reasons, copper has been the favorite starting material; however, the copper price has recently been climbing sharply.

In recent years, a number of technical and market trends have made it more and more difficult to find satisfactory solutions for the diverse requirements.

Then, the requirement to use lead-free solders pushes the reflow temperature range into the neighborhood of about 260° C., making it more difficult to maintain mold compound adhesion to the leadframes.

ICs are becoming faster; consequently, they dissipate more thermal energy, which needs to be removed to maintain optimum operating temperatures.

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