Storage controller, data processing method and computer program product

Abstract

When a first channel processor from among a plurality of channel processors receives an I / O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I / O request, is selected from among the channel processors based on the LM directories of the respective channel processors. The selected second channel processor checks whether there is a cache hit. If there is a cache hit, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I / O request using the data transferred to the buffer memory.

Description

CROSS REFERENCES TO RELATED APPLICATIONS [0001] This application relates to and claims priority from Japanese Patent Application No. 2005-267184, filed on Sep. 14, 2005, the entire disclosure of which is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention relates to a storage controller, data processing method and a computer program product. [0003] Lately, disk array apparatuses have been used as storage systems for managing large amounts of data. A disk array apparatus, having a number of disk drives arranged in arrays, provides host systems with storage resources, which together form a RAID (Redundant Arrays of Independent Inexpensive Disks) structure. A storage area network (SAN) environment using Fibre Channel (FC) protocol as an interface for network-connecting the host systems and the disk array apparatus has become popular. The disk array apparatus connected to the host systems via the SAN is equipped with channel control units for recei...

AI Technical Summary

Benefits of technology

The present invention is a storage controller that reduces channel processor overhead to speed up the Fibre Channel interface. It achieves this by efficiently managing cache slots and processing data from cache memory. The controller has multiple channel processors, a cache memory, a local memory, and a buffer memory. When a first channel processor receives an I / O request from the host system, it selects a second channel processor to execute a part of the processing based on the management information indicating whether or not data read and written by the relevant channel processor exists in the cache slot. The second channel processor checks whether there is a cache hit and, if there is, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I / O request using the data transferred to the buffer memory. This reduces the cache hit rate of the second channel processor and the channel processor overhead caused by cache slot management and data transfer. The storage controller according to the present invention achieves efficient cache management and reduces channel processor overhead.

Problems solved by technology

However, in a conventional disk array apparatus, although there are plural channel processors provided in a channel control unit, an I / O request received via a port from a host system is processed by only one channel processor, therefore, resources of the rest of the channel processors are not utilized effectively.

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