Line level air gaps

Abstract

In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Description

RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10 / 731,377, filed Dec. 8, 2003.BACKGROUND OF THE INVENTION [0002] The present invention relates to high density multilevel microelectronic integrated circuit (IC) structures. In particular, the present invention relates to the reduction of dielectric constant between conductive lines in each line level by providing air dielectric. A porous permanent dielectric in via levels is provided in order to optimize further the performance of the structure in a functioning device. [0003] An aggressive drive continues toward increasing the density of features in the IC structure and toward decreasing the size of individual features. At present, feature dimensions can be fabricated to be as small as about 0.5 microns or less, and may be separated by less than 5000 Angstroms. As the drive continues, materials and processes by which the IC structure is composed must be reexamined in order to deal with proble...

AI Technical Summary

Benefits of technology

[0011] The present invention provides a process and structure which results in a mechanically stable IC in a way that avoids processing problems experienced in the art. This result is accomplished by having air dielectric at line levels where the metallization is dense and a low-K dielectric environment is most required, in combination with low-K gas-permeable solid or porous permanent dielectric material at via levels to provide mechanical stability. The present invention does not include removal of sacrificial material by oxygen ashing or oxygen plasma etch or a reactive ambient lest the copper wiring lines be adversely affected. The present invention is directly compatible with the dual damascene process for the fabrication of copper wiring lines which is currently the state of the art.

[0015] After heat treatment, a non-gas permeable etch stop is deposited on the via level and cured in order to protect the via and metallization levels from any contamination that might be generated in the sequential processing of additional layers. The process is repeated to fabricate additional via and line levels, as required. The IC of the present invention will provide Back End of Line (BEOL) interconnects with the lowest possible effective K in the line level where it has the biggest impact on RC delay, balanced with the most robust mechanical stability.

Problems solved by technology

A major problem with increased density is the increased intralevel interaction in capacitive voltage coupling and cross-talk between conductive lines, the largest component of which is between adjacent conductive lines in a given line level.

As a result of this increased interaction, the IC is at great risk for failure at line level, in the form of unacceptably slow signal propagation, i.e. Resistance-Capacitance (R-C) delay and increased energy consumption.

While these materials all have low K, the value is not as low as the ideal value of air and, as described in the Nag et al. patent, each may come with its own alternate limitations when left as the wiring level dielectric.

The presence of a liner on the wiring, however, risks raising the effective K. In U.S. Pat. No. 6,350,672 B1 to Sun there is no liner described.

Some wiring, however, such as copper, would be attacked by oxygen ash or oxygen plasma etch.

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