Semiconductor device and method of fabrication thereof

Abstract

A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to semiconductor devices and methods of fabrication thereof and particularly to those utilizing self-aligned shallow trench isolation (SA-STI) for forming a gate electrode and an active region simultaneously. [0003] 2. Description of the Background Art [0004] For flash memory, self-aligned shallow trench isolation (SA-STI) has conventionally been employed. SA-STI allows a floating gate electrode's polysilicon and a shallow trench isolation (STI) to be formed with a single mask in self alignment. This technique has the following advantages: [0005] First, the STI is formed after a tunnel insulation film (or gate insulation film) is provided. This can prevent the tunnel insulation film from falling in at an end of an active region and thus thinning as typical STI would not avoid. As such, SA-STI can enhance the tunnel insulation film in reliability. [0006] Second, a trench and a ...

AI Technical Summary

Benefits of technology

[0015] The present invention contemplates a nonvolatile memory device and a method of fabrication thereof that can ensure a tunnel insulation film's characteristic(s) and in addition prevent Vth distribution from having increased ranges after erasure operation and, in a particular case, in addition thereto improve device operation performance.

[0017] By the above described method the first silicon layer of polysilicon can have crystal grains that are not increased in size to be unsuitable for practical use and the impurity in the second silicon can also be thermally diffused into the first silicon layer. As a result, Vth after erasure operation can have a distribution prevented from expansion in width and the first silicon layer can also have the impurity at a concentration controlled as appropriate to provide improved device operation performance.

[0020] Thus the first polysilicon layer can be prevented from having crystal grains increased in size, and Vth after erasure operation can have a distribution prevented from expansion in width. As a result, disadvantageously increased periods of time otherwise required to recover an overerased bit can be resolved.

Problems solved by technology

However, the first silicon layer itself is deposited in a method selected as appropriate and at a temperature selected as appropriate, and a tunnel insulation film that contacts the first silicon layer thus deposited is impaired in characteristic.

As a result, device characteristics, reliability and the like can be impaired.

For example if the first silicon layer is implemented by a polysilicon film deposited at at least 600° C. to have a small thickness of at most 20 nm, it tends to be substantially all defective in withstand voltage because of a tunnel oxide film's defect.

The increased crystal grain size is promoted for example by a gate's dimensional variation and causes disadvantageously varying distribution of Vth (a value in voltage of a threshold of a transistor) after erasure operation.

As such, when the chip is seen as a whole, post-erasure Vth distribution has an increased range and recovering an overerased bit requires time, and erasure operation cannot be completed in a short period of time.

Furthermore, if the recovery requires a significantly long period of time, disadvantageously reduced yield can be provided.

If the first silicon layer is formed of P doped amorphous silicon, however, an increased crystal grain size is provided regardless of film thickness and a problem similar to that described above arises.

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