Differential pipelined analog to digital converter with successive approximation register subconverter stages

Abstract

Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs. In one implementation, the capacitors are switched according to a thermometer code to reduce differential converter non-linearity, and the first subconverter stage gain is reduced to improve the conversion system bandwidth.

Description

FIELD OF INVENTION The present invention relates generally to signal processing, and more particularly to a pipeline analog to digital data converter having pipelined fully differential multi-bit successive approximation register subconverter stages. BACKGROUND OF THE INVENTION Wireless communications products and other modern electronic devices typically process and generate both digital and analog signals. To perform their intended functions, these systems often convert analog signals into digital signals, referred to as analog to digital (A / D) conversion. Accordingly, these systems require circuitry to interface signals from the analog domain to signals in the digital domain so that they may perform further digital signal processing. In particular, analog to digital conversion systems (A / D converters, or ADCs) are needed to interface the analog and digital domains. Advances in wireless communications devices, DVD systems, and other related technologies indicate a need for incr...

AI Technical Summary

Benefits of technology

The invention is about a system for analog to digital conversion using multi-bit SAR subconverter stages. The system has high conversion speed and low power consumption, and is more efficient than conventional flash converters and non-pipelined designs. The first subconverter stage uses a thermometer code to selectively couple capacitors to the input and output nodes, reducing differential non-linearity. The second subconverter stage has a higher gain factor to compensate for the reduced range of the residue output signal. The subconverter stage capacitors have equal capacitance values, and the use of thermometer coding reduces differential non-linearity compared to binary coding techniques. The invention provides a simplified understanding of the analog to digital conversion system and its advantages.

Problems solved by technology

At the same time, however, power consumption is an important design consideration, wherein portable devices need to perform high-resolution analog to digital conversions while consuming a minimal amount of power.

However, flash converters require a large number of comparator circuits.

As a result, flash type converters occupy a large amount of area in an integrated circuit, and also consume a relatively high amount of power.

However, these conventional pipelined flash converter systems 10 still occupy a relatively large amount of die area, due at least in part to the provision of 2M comparator circuits 52 in each stage 12, and the system 10 consumes a considerable amount of power.

Images