Delay locked loop circuit

Abstract

A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Description

technical field [0001] The present invention relates to a delay locked loop circuit; more particularly, the present invention relates to a method for controlling the output of a delay locked loop circuit in a synchronous dynamic random access memory (SDRAM) based on an operating condition such as pressure or temperature memory device. Background technique [0002] In general, a delay locked loop (DLL) is a circuit for controlling the timing of output data from a semiconductor memory device such as a dynamic random access memory (DRAM) to an external device by using an external input clock signal. In order to transfer data from a semiconductor memory device to a chipset or a CPU without any error, the output of the semiconductor memory device is synchronized with a clock signal generated from the chipset or the CPU. [0003] When a clock signal is transferred to / from an internal control block in a semiconductor memory device, the clock signal is delayed due to input clock bu...

AI Technical Summary

Problems solved by technology

However, if the operation margin of the DLL output clock decreases under high-frequency operation or changes in operating conditions such as pressure, temperature, or input voltage potential, when one DLL output clock with one phase is used to control multiple control circuits , the operational reliability of the semiconductor memory device decreases

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