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Semiconductor imaging device and fabrication process thereof

A technology of imaging devices and semiconductors, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as rising and not reading signals

Inactive Publication Date: 2007-01-31
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In response to the rise of the reset signal, the potential of the floating diffusion FD rises at the same time, and the influence of this rise in potential of the floating diffusion FD is also transferred via the read transistor 10F and the selection transistor 10S which are in the on state. to signal line SIG, however note that this rise in signal line SIG is not used to read signal

Method used

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  • Semiconductor imaging device and fabrication process thereof
  • Semiconductor imaging device and fabrication process thereof
  • Semiconductor imaging device and fabrication process thereof

Examples

Experimental program
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no. 1 example

[0094] Figure 8 It is a schematic diagram showing the cross-sectional structure of the semiconductor imaging device 40 according to the first embodiment of the present invention, wherein the semiconductor imaging device 40 corresponds to figure 2 Transistor 10C and photodiode 10D of the CMOS imaging device.

[0095] refer to Figure 8 , the semiconductor imaging device 40 is formed in the p-type device region 41A defined on the silicon substrate 41 by the STI device isolation structure 41I, wherein corresponding to the channel region formed in the device region 41A, on the silicon substrate 41 via the usual A polysilicon gate electrode 43 is formed of a gate insulating film 42 which is a thermal oxide film.

[0096] In the active region 41A, an n-type diffusion region 41D is formed on the first side of the gate electrode 43 as a photodetection region of the photodiode 10D, and a p-type diffusion region 41D is formed on a surface portion of the diffusion region 41D. + Type...

no. 2 example

[0123] Figure 13A and 13B To illustrate the second embodiment according to the present invention Figure 10B A schematic diagram of a modification of the ion implantation process, while Figure 14 to show the basis Figure 13A and 13B A schematic diagram of the semiconductor imaging device 40A fabricated by the process.

[0124] refer to Figure 13A and 13B , this example will be in Figure 10B In the step of forming the p-type diffusion region 41P2, the thickness of the resist pattern R2 formed on the silicon substrate 41 is set to about 1 μm, and the surface of the n-type diffusion region 41D is at least two directions at an angle of 7 degrees. B + ion implantation.

[0125] In this case, as Figure 13B As shown, the dose of ion implantation is reduced in a shadow portion of the resist pattern R2, and a region 41pm having an intermediate impurity concentration level is formed between the p-type region 41P2 and the p-type diffusion region 41P1.

[0126] Thus, in ...

no. 3 example

[0131] Figure 15A and 15B A manufacturing process of the semiconductor imaging device 40B according to the third embodiment of the present invention is shown, wherein those parts corresponding to the foregoing parts are denoted by the same reference numerals, and their descriptions are omitted.

[0132] Figure 15A It is shown that the p-type diffusion region 41P2 is formed at a shallower level than the p-type diffusion region 41P1 Figure 10B The corresponding process of the process. For example, in Figure 15A In the step, while using the resist pattern R2 as a mask, the acceleration voltage is 8-15keV, the dose is 0.5-3.0×10 12 cm -2 And under the condition that the angle is 7 degrees, the B+ ion implantation process is performed in the relationship of overlapping with the n-type diffusion region 41D.

[0133] Due to this ion implantation process, such as Figure 15B shown in Figure 10C In the structure obtained after the step of , the p-type region 41P2 is formed...

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Abstract

A semiconductor imaging device, comprising: a photodetection region formed of a diffusion region of a first conductivity type and formed in an active region of a silicon substrate on a first side of a gate electrode so that its top is in contact with the silicon substrate and the inner edge portion invades under the channel region directly below the gate electrode; a shielding layer formed of a diffusion region of the second conductivity type and on the surface of the silicon substrate on the first side of the gate electrode, thereby The inner edge portion thereof is aligned with the side wall surface of the gate electrode on the first side; a floating diffusion region is formed in the active region on the second side of the gate electrode; and a channel region is formed on the second side of the gate electrode. directly below the gate electrode, wherein the channel region includes: a first channel region portion formed adjacent to the shielding layer; and a second channel region portion formed adjacent to the floating diffusion region, wherein the second The channel region portion contains impurity elements at a concentration level lower than that of the first channel region portion.

Description

[0001] Cross References to Related Applications [0002] This application is based on Japanese Priority Application No. 2005-220131 filed on July 29, 2005, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention generally relates to semiconductor devices, and more particularly to a semiconductor photodetection device constituting a CMOS imaging device. Background technique [0004] Today, CMOS imaging devices are widely used in cellular phones with video cameras, digital cameras, and the like. CMOS imaging devices are characterized advantageously over CCD imaging devices in that they are simple in structure and can be produced at low cost. [0005] figure 1 The structure of such a CMOS imaging device 100 is shown. [0006] refer to figure 1 , CMOS imaging device 100 includes photodetection area 101A, in photodetection area 101A a large number of CMOS pixel elements 10 are arranged in rows and columns, wherein row ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/146H01L21/822
CPCH01L27/14603H01L27/14601H01L27/14623H01L27/146
Inventor 大川成实
Owner FUJITSU SEMICON LTD
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