Method for realizing kernel-mode programe verification in user-mode random verification of microprocessor

Abstract

The present invention discloses method for realizing kernel mode program verification method in microprocessor user status random verifying. Said method includes 1, adding exception handling correlative restriction in instruction stencil-plate; 2, improving instruction grade random verifying generation engine; 3, adding kernel mode instruction execution mechanism instruction grade processor simulator, setting register, providing right result in system running kernel mode instruction; 4, adding step 1 added correlative restrictive filtering unit in instruction filter; 5, adding abnormal monitoring logic and control register updating logical in emulation environment; 6, pre-storing exception handler in emulation environment provided memory. The present invention has advantages of complete verifying and high verifying efficiency.

Description

technical field [0001] The microprocessor verification technology of the present invention particularly relates to a method for realizing program verification of a core state in random verification of a microprocessor user state. Background technique [0002] Analog emulation is a common method for processor verification. Extensive coverage of test vectors is very important when performing simulations. A variety of methods can be used to generate test vectors, among which the main methods include instruction set random test generation, hand-written test vectors and application program encapsulation. [0003] Many RISC architecture processors can run instructions in multiple modes, and use different address spaces according to different operating modes. Taking MIPS CPU as an example, a MIPS CPU can run instructions in two priority levels: user mode and kernel mode. Taking MIPS R4000 as an example, the available space of user mode in 32-bit mode is 0x00000000~0x7fffffff, a ...

AI Technical Summary

Problems solved by technology

The method of handwriting test vectors enumerates the instructions of the core state and the various states of the control registers, and uses experts to manually write the test vectors for each test point. The biggest disadvantage of this method is that it consumes a lot of manual labor and is inefficient. At the same time, Since the state combinations of core state instructions and control registers are very complex and difficult to enumerate, it is difficult for handwritten test vectors to evenly cover all test points

Obviously, only relying on handwritten test vectors and some application packaged test vectors cannot complete the full verification of processor core state instructions

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