Solder interconnect structure and method using injection molded solder

Abstract

Improved interconnects are produced by injection molded solder which fills mold arrays with molten solder so that columns that have much greater height to width aspect ratios greater than one are formed, rather than conventional flip chip bumps. The columns may have filler particles or reinforcing conductors therein. In the interconnect structures produced, the cost and time of a subsequent underfill step is reduced or avoided. The problem of incompatibility with optical interconnects between chips because underfills require high loading of silica fillers which scatter light, is solved, thus allowing flip chips to incorporate optical interconnects.

Description

Technical field [0001] The present invention relates to the field of solder interconnections formed between a circuit device and a substrate forming the next level of electrical interconnection. In particular, the present invention relates to improvements in the injection molding solder technology used to form solder bump interconnections generally on silicon wafers. Background technique [0002] Semiconductor chips are usually connected to other circuits using solder bumps with a diameter of about 100 microns. These solder joints suffer from thermal fatigue failure because of the difference in coefficient of thermal expansion (CTE) between the silicon and the chip carrier that holds them. Using injection molding solder (IMS) technology, solder interconnections can be fabricated on semiconductor chips or chip carriers with controlled shapes and compositions, thereby extending the fatigue life of the joint. Therefore, the present invention aims to improve the solder interconnectio...

AI Technical Summary

Problems solved by technology

Second, the increase in silicon chip size also limits the ability of underfill to enhance conventional ball solder interconnects

Third, the power required for silicon devices increases, especially for microprocessor chips; and conventional solder interconnects are unlikely to withstand the high currents required to deliver this power

This relieves the stress on the solder bump itself, but adds a processing step, which is time consuming and adds cost

As signal and power demands increase, the smaller spherical size of each bump does not allow adequate isolation between the chip and substrate, which has two detrimental effects

First, capillary underfill processes become slow or infeasible; second, increased mechanical stress due to CTE mismatch

In addition, such underfill layers are generally opaque, thus preventing optical communication between the bottom of chip 20 and substrate 22, as desired in advanced packaging schemes

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