Extensible high-radix Montgomery's modular multiplication algorithm and circuit structure thereof

Abstract

The invention relates to an extended high base Montgomery analog multiplying algorithm and the circuit structure in the field of integrated circuit technology. It improves multiply characters high base Montgomery analog multiplying algorithm, wherein each step dose left shift operation to the batch N and the multiplicand B but not to the result S so that the delay between the two data path lines can de reduced from two clock weeks to one clock week. The circuit structure comprises: three storages used to store A, B and N operation numbers, a line type data path module which is formed by first stage to p stage processing units, a control module used to control the entire analog multiplier computing course and first-in first-out storage.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an improved scalable high-base Montgomery (Montgomery) modular multiplication algorithm and a circuit structure thereof. Background technique [0002] With the rapid development of electronic communication technology, people pay more and more attention to information security. In order to ensure the security of transmitted data, many cryptographic algorithms and protocols have been proposed. Because implementing encryption algorithms with software is time-consuming and has security risks, the hardware implementation of RSA and other cryptographic algorithms has become a hotspot in the research of information security technology in recent years. Many domestic and foreign scholars have achieved many research results in this area, and there are Many results are applied to various information security products. [0003] Finite field multiplication is widely ...

AI Technical Summary

Problems solved by technology

[0039] The problem with the above-mentioned multi-word high-base Montgomery modular multiplication algorithm is that if the pipeline circuit structure of multi-level processing units is adopted, because S (i-1) Passed to the next level operation must wait until S (i) k-1..0 Calculated, so the data is transferred from the upper-level pipeline to the next-level pipeline after a delay of two clock cycles, which leads to a slowdown in the speed of the modular multiplication operation

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