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Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus

A manufacturing method and semiconductor technology, which can be used in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., and can solve problems such as difficulty in bonding bumps and large surface roughness of bumps.

Inactive Publication Date: 2005-10-19
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] As mentioned above, Au bumps are used for fine connections, but it is difficult to bond these bumps to each other due to the roughness of the bump surface
In addition, in the case of using CMP to simultaneously planarize a metal such as Au and a resin, pits called dishing occur due to differences in polishing speeds of the metal and the resin.

Method used

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  • Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
  • Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
  • Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus

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no. 1 approach

[0058] Here, a silicon semiconductor substrate is exemplified as a substrate, and a method of forming bumps provided for electrical connection with the outside on the semiconductor substrate, a semiconductor device using this method, and a manufacturing method thereof.

[0059] (Bump forming method)

[0060] Figure 1A ~ Figure 1D , Figure 2A , Figure 2B It is a schematic cross-sectional view showing the bump forming method according to this embodiment in order of steps.

[0061] First, a silicon semiconductor substrate 1 is prepared, and a desired LSI semiconductor element (not shown) is formed on an element formation site on the substrate surface 1a. Hereinafter, each step will be described with respect to the semiconductor substrate 1 in which LSI semiconductor elements and the like are formed on the element formation site in this way.

[0062] Such as Figure 1A As shown in the figure, the silicon semiconductor substrate is generally in a state of varying thickness w...

no. 2 approach

[0093] Next, a second embodiment will be described. In the first embodiment, Au was exemplified as the bump material, but the case of using nickel (Ni) is exemplified in this embodiment.

[0094] Figure 10A ~ Figure 10F It is a schematic cross-sectional view showing the bump forming method according to this embodiment in order of steps.

[0095] First, after the comparison with the first embodiment Figure 1A In the same process as B and B, the back surface of the semiconductor substrate 1 is ground, and the TTL is controlled to a predetermined value or less, specifically 1 μm or less.

[0096] Using this semiconductor substrate 1, as Figure 10A As shown, after the electrode 31 made of aluminum-based metal is patterned on the surface of the semiconductor substrate 1, a nickel-phosphorus plating film 32 with a film thickness of about 5 μm to 10 μm is formed on the electrode 31 by electroless plating.

[0097] The nickel-phosphorus plating film 32 is formed using nickel-ph...

no. 3 approach

[0110] Next, a third embodiment will be described. In the first embodiment, the case where a plurality of semiconductor chips are bonded to the semiconductor substrate was exemplified, but this embodiment discloses a case where the above-mentioned planarization process is performed in the state of the semiconductor chips, and the semiconductor chips are bonded together. .

[0111] Figure 11A , Figure 11B It is a schematic sectional view showing the manufacturing method of the semiconductor device according to this embodiment in order of steps.

[0112] First, if Figure 11A As shown, the backside grinding of the first embodiment is unnecessary, and the individual semiconductor chips 41 are cut out from the semiconductor substrate on which LSI elements and the like are mounted, and a plurality of bumps having different heights (there are still deviations in height) are formed, These are Au bumps 42 here.

[0113] Next, the surface layer of the semiconductor chip 41 is ma...

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Abstract

The rear (1b) of a semiconductor substrate (1) is fixed to the support face (11a) of a substrate support base (11) by vacuum clamping. The thickness of the semiconductor substrate (1) is uniform by planarizing the rear (1b), and the rear (1b) is forcedly free of waviness caused by the vacuum clamping to the support face (11a), so that the rear (1b) functions as the reference face of the planarization of the front (1a). In this state, Au projections (2) on the front (1a) and the surface layer of a resist mask (12) is cut with a single point tool (10) to planarize the surface of Au projections (2) and that of the resist mask (12) so as to be flat continuously. Thus, instead of CMP, the surface of a fine bump formed on a substrate is planarized at low cost low costly and speedily.

Description

technical field [0001] The present invention relates to a method of forming fine bumps for electrical connection with the outside on the surface of a substrate, a semiconductor device and its manufacturing method, a substrate processing apparatus, and a semiconductor manufacturing apparatus. Background technique [0002] Conventionally, gold (Au) bumps or the like have been used as fine metal terminals on the surface of a semiconductor substrate for electrical connection to the outside. The Au bump is formed by electroplating, and has a large surface roughness. In order to planarize such metal terminals, a chemical mechanical polishing (CMP) method is used. In this method, relatively flat metal and resin to be processed are formed in advance, and after contacting the flat polishing pad, the processed surface is chemically and mechanically finely flattened using a slurry (chemical polishing material). The pre-set hard resin or metal surface becomes the stop layer, thus endi...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L21/60
CPCH01L2924/01074H01L2924/01006H01L2224/75H01L2224/83191H01L2924/00013H01L2924/01004H01L2224/48227H01L24/11H01L2924/01082H01L2924/3025H01L2924/01027H01L2224/48091H01L2924/01015H01L24/45H01L2924/01005H01L2924/01033H01L2924/01047H01L2924/01019H01L2924/01079H01L21/4853H01L2224/1134H01L2224/29298H01L2224/45144H01L2224/16145H01L2924/01013H01L2924/01018H01L2924/014H01L2924/01078H01L2224/13099H01L24/29H01L2924/01014H01L2924/01039H01L2224/749H01L2224/48465H01L2924/01023H01L2924/0781H01L2924/0105H01L2224/13147H01L2924/01029H01L2224/75252H01L2224/13144H01L2924/01011H01L2224/838H01L24/83H01L2924/01028H01L2924/0103H01L2224/1184H01L2224/45015H01L2224/73104H01L2924/15788H01L2924/00014H01L2924/00H01L2224/29099
Inventor 水越正孝石月义克中川香苗冈本圭史郎手代木和雄酒井泰治
Owner FUJITSU LTD
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