Wiring design device and method for integrated circuit

Abstract

An apparatus executes wire layout design in an integrated circuit. The apparatus includes a logic cell arrangement information acquisition unit which acquires information concerning a logic cell arrangement on a chip, a wire-grouping unit which estimates wires between logic cell terminals based on the acquired information and groups the estimated wires into each wire layer region, a via setting unit which sets via wire for pulling a logic cell terminal up to a wire layer region, a wire information extraction unit which extracts wire information for each of the wire groups and a routing execution unit which executes routing between the logic cell terminals for each of the wire layer regions based on the extracted information. A method for executing wire layout design in an integrated circuit includes acquiring information concerning a logic cell arrangement on a chip, executing wire-grouping, setting via wire for pulling a logic cell terminal up to a wire layer region, extracting wire information for each of the wire groups, and executing routing between the logic cell terminals for each of the wire layer regions based on the extracted information. The wire-grouping contains estimating wires between logic cell terminals based on the acquired information concerning the logic cell arrangement and dividing the estimated wires into each group of a wire layer region.

Description

[0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2002-138399 filed on May 14, 2002, the entire contents of which are incorporated herein by reference. technical field [0002] The present invention relates to semiconductor integrated circuit design, and in particular to a semiconductor integrated circuit design device, a semiconductor integrated circuit design method, and a semiconductor integrated circuit design program used in the wiring layout design process between logic cells. Background technique [0003] The layout design process, which is an important process in system LSI design, requires the use of wiring connection information obtained from logic design and a logic cell library prepared through circuit design to configure logic gates and automatically route wiring to make the chip area as small as possible. [0004] In recent years, with the increase in the scale of integrated circuits, the informat...

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Problems solved by technology

[0006] However, 1) In the method of uniformly wiring the entire chip, since the wiring connection information of the entire chip is processed at the same time, the amount of memory usage increases and the processing time becomes longer.

Therefore, when the scale of the integrated circuit is large, there are problems of inability to layout and long design time due to insufficient memory.

[0007] On the other hand, 2) In the hierarchical layout method, since the necessary memory usage can be limited, the problem of the memory usage when performing unified wiring is solved, but since the logic module area is set as a wiring-prohibited area, the limitation The degree of freedom of wiring is increased, and the chip area becomes larger as a result

In addition, since each module is processed independently, it is difficult to meet the timing constraints of the wiring across the modules and the processing antenna constraints caused by the influence of the charge accumulated between the wiring layers generated in the device manufacturing process at the design stage. Chip design time tends to be long

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