Method for producing semi-conductor

Abstract

The present invention provides a method for producing semi-conductor. The inventive method includes the steps of: forming a plurality of patterns on a substrate, wherein the patterns are formed by stacking and patterning a first conductive layer, a silicon nitride mask layer and a metal mask layer on the substrate; depositing a first silicon oxide layer along the profile containing the patterns; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer, wherein the metal mask layer prevents losses of the silicon nitride mask layer; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole that is partially expanded to the top portion of the patterns; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device; in particular, a method for reducing the parasitic capacitance of a semiconductor storage unit. Background technique [0002] As the integration level of semiconductor devices increases, it is more difficult to achieve the overlay accuracy and process tolerance of the pattern forming process by using a photoregistry. Therefore, a self-aligned contact (hereinafter referred to as SAC) process is particularly adopted and suitable for solving this problem. The SAC process is an etching process that etches objects by using the previously deposited material itself rather than an applied mask. Because of this feature, the SAC process can significantly reduce the cost of manufacturing semiconductor devices. The SAC process itself uses several methods to achieve efficient etching, and among these various methods, a nitride layer is typically used as an etch stop layer. [0003] There...

AI Technical Summary

Problems solved by technology

[0013] However, it is recommended to implement figure 1 In Korean Patent Application Laid-Open Publication No. 2000-0048819 of the shown method, it discloses the difficulty of forming each conductive pattern, for example, the silicon oxide layer spacers on the lateral sides of the bit lines, whose height is lower than that of the silicon nitride layer. top of the structured mask layer, since the etch selectivity ratio between the silicon oxide layer and the silicon nitride layer is not as high as in an actual wafer with micro

In other words, the mask layer constructed from the silicon nitride layer will inevitably be damaged during the processing steps, so the application in the actual process is not feasible

Images