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Hybrid NVME SSD storage system based on MRAM cache

A storage system and hybrid technology, applied in information storage, static memory, digital memory information, etc., can solve the problems of 3DTLC NAND high error rate, FTL mapping table loss, SSD cannot be recognized by the system, etc., to achieve a wide range of application scenarios, good Effect of Delayed Determinism and Guaranteed Reliability

Pending Publication Date: 2022-07-29
SHANDONG SINOCHIP SEMICON
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  • Abstract
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  • Claims
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Problems solved by technology

[0003] NAND FLASH is used as the non-volatile memory in the current NVME SSD, but when NAND FLASH is applied, it is necessary to complete the development of SSD software code in combination with its usage restrictions
At the same time, due to the high error rate of 3D TLC NAND, BCH cannot solve it, so LDPC must be used
In addition, if an abnormal power failure occurs when the SSD is reading, writing, deleting, etc., it may cause the FTL mapping table to be lost because it is too late to update, resulting in a failure that the SSD cannot be recognized by the system

Method used

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  • Hybrid NVME SSD storage system based on MRAM cache

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Embodiment 1

[0023] This embodiment discloses a hybrid NVME SSD storage system based on MRAM cache, which improves the random performance and reliability of the NVME SSD controller in a targeted manner, ensures data security, solves the problem of power failure protection, and reduces power failure recovery time.

[0024] like figure 1 As shown, the system includes SSD controller, volatile storage layer and non-volatile storage layer, SSD controller includes PCIe interface, NVME command parser, FTL mapping manager, NAND controller, MRAM controller and DRAM controller, The volatile storage layer includes external DRAM, and the non-volatile storage layer includes external NAND and external MRAM. The PCIe interface, NVME command parser, and FTL mapping manager are connected in sequence. The NAND controller, MRAM controller, and DRAM controller are all connected to The FTL mapping manager is connected, the external DRAM is connected to the DRAM controller, the external NAND is connected to the...

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Abstract

The invention discloses a hybrid NVME SSD storage system based on MRAM cache, which comprises an SSD controller, a volatile storage layer and a nonvolatile storage layer, the SSD controller comprises a PCIe interface, an NVME command parser, an FTL mapping manager, an NAND controller, an MRAM controller and a DRAM controller, the volatile storage layer comprises an external DRAM, the nonvolatile storage layer comprises an external NAND and an external MRAM, the external NAND is connected with the external MRAM, and the external NAND is connected with the external MRAM. The PCIe interface, the NVME command parser and the FTL mapping manager are sequentially connected, the NAND controller, the MRAM controller and the DRAM controller are all connected with the FTL mapping manager, the external DRAM is connected with the DRAM controller, the external NAND is connected with the NAND controller, and the external MRAM is connected with the MRAM controller. According to the method, the random performance and reliability of the NVME SSD controller can be improved, the data security is guaranteed, the problem of power failure protection is solved, and the power failure recovery time is shortened.

Description

technical field [0001] The invention relates to the field of mobile storage, in particular to a hybrid NVME SSD storage system based on MRAM cache. Background technique [0002] NVME is a host controller interface specification for non-volatile memory. At present, it is widely used in the application layer protocol implemented by the PCIExpress bus to connect with the non-volatile storage medium. Compared with the maximum 32 sets of command queues provided by traditional SATA SSDs, NVME SSDs provide thousands of parallel queues to control IO data streams, which can greatly reduce latency and greatly improve the IOPS capability of SSDs. [0003] The current NVME SSD uses NAND FLASH as non-volatile memory, but when NAND FLASH is applied, it is necessary to complete the development of SSD software code in combination with its usage restrictions. At the same time, because the error rate of 3D TLC NAND is too high, BCH cannot solve it, and LDPC must be used. In addition, if an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/401G11C29/42
CPCG11C11/401G11C29/42
Inventor 刘奇浩沈力李瑞东
Owner SHANDONG SINOCHIP SEMICON
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