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Low-power-consumption readout circuit based on folding comparator and control method

A technology for reading circuits and comparators, applied in instruments, static memory, digital memory information, etc., to achieve the effects of small hardware consumption, increased output swing and gain, and improved reliability

Active Publication Date: 2015-07-22
铠强科技(平潭)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, using the folded cascode comparator alone will generate additional static power consumption when it is not working, which greatly increases the total power consumption of the entire reading circuit.

Method used

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  • Low-power-consumption readout circuit based on folding comparator and control method
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  • Low-power-consumption readout circuit based on folding comparator and control method

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Experimental program
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Embodiment Construction

[0026] The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

[0027] Such as Figure 1-7As shown, the present invention is a low-power reading circuit based on a folding comparator, including a folding cascode comparator and a control circuit connected to the folding cascode comparator, a parallel magnetic tunnel junction, A control logic circuit and an inverter, the control circuit is connected to the parallel magnetic tunnel junction, the inverter is also connected to a first D flip-flop and a second D flip-flop, and also includes a clock output module, the The first clock signal output end and the second clock signal output end of the clock output module are respectively connected to the clock control input ends of the first D flip-flop and the second D flip-flop; the folded cascode comparator includes The first to eleventh MOS transistors, the source of the first MOS transistor and the source o...

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PUM

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Abstract

The invention relates to a low-power-consumption readout circuit based on a folding comparator and a control method. The readout circuit comprises a folding cascade comparator, and a control circuit, a parallel magnetic tunnel junction, a control logic circuit and a phase inverter which are connected with the folding cascade comparator, wherein the control circuit is connected with the parallel magnetic tunnel junction; the phase inverter is further connected with the a first D trigger and a second D trigger; the readout circuit further comprises a time output module; the first clock signal output terminal and the second clock signal output terminal of the time output module are respectively connected with the clock control input terminals of the first D trigger and the second D trigger. The readout circuit can effectively improve the readout speed, reduces the power consumption of operating circuit during stand-by time by adding the control circuit, increases the output range and gain, and improves the reliability of the whole readout circuit when the readout circuit is butted with a digital system.

Description

technical field [0001] The invention relates to a low power consumption reading circuit and a control method based on a folding comparator. Background technique [0002] Traditional Random Access Memory (RAM) such as Dynamic Random Access Memory (DRAM) is relatively inexpensive, but has slower access speeds, poor durability and data can only be stored for a short period of time. Since the data must be refreshed once in a while, this in turn leads to higher power consumption. Static random access memory (SRAM) has the advantages of fast access speed, low power consumption, and non-volatility, but it is expensive and has low integration. [0003] In recent years, the emerging spin transfer torque random access memory (STT-RAM) is expected to become the first choice for future caches due to its high density, low leakage current, non-volatility, ultra-long durability, and fast read and write. product. [0004] This patent is based on a novel tree-type reading circuit scheme, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/16
CPCG11C11/161G11C11/1673G11C11/1693
Inventor 魏榕山刘德鑫林心禹于静王珏张泽鹏
Owner 铠强科技(平潭)有限公司
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