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Router delay model, establishment method and network-on-chip routing algorithm based on router delay model

A router and model modeling technology, applied in transmission systems, electrical components, etc., to solve problems such as path congestion and uneven traffic distribution

Active Publication Date: 2022-05-06
XIDIAN UNIV
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Problems solved by technology

[0005] The purpose of the present invention is to propose a router delay model for routers based on virtual channels, and apply it as a standard for measuring node congestion In the routing algorithm, the congestion value of the network path is obtained in real time through Q reinforcement learning to solve the problem of path congestion caused by unequal traffic distribution in the on-chip network

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  • Router delay model, establishment method and network-on-chip routing algorithm based on router delay model
  • Router delay model, establishment method and network-on-chip routing algorithm based on router delay model
  • Router delay model, establishment method and network-on-chip routing algorithm based on router delay model

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Embodiment Construction

[0059] The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation modes of the present invention will be described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Example. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative efforts shall fall within the protection scope of the present invention.

[0060] In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled i...

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Abstract

As the scale of an integrated circuit is increased, the communication complexity of a network-on-chip is continuously improved, and the network performance is seriously influenced by the congestion problem caused by network hotspots and the like. How to measure the network congestion degree to avoid congestion nodes is a key problem in a network-on-chip adaptive routing algorithm. The invention provides a router time delay model, a building method and an on-chip network routing algorithm based on the router time delay model, the total time delay value of data from entering into a router node to leaving from the router node is evaluated, the router time delay model is built on the basis and serves as a standard for measuring node congestion, and a Q-learning reinforcement learning routing algorithm based on the router time delay model is provided. According to the routing algorithm provided by the invention, the latest global network state can be obtained in real time, the data can avoid a network congestion area, and the network performance is improved.

Description

technical field [0001] The invention relates to an on-chip network routing algorithm, in particular to an on-chip network routing algorithm based on a router delay model. Background technique [0002] With the continuous development of integrated circuit technology, the number of transistors increases exponentially, which brings many challenges to the development of System on Chip (SoC). The communication architecture based on the traditional bus has low communication efficiency, poor scalability and reusability, which limits the continuous growth of chip performance. Network-on-Chip (NoC) refers to the distributed computer communication method, adopts point-to-point routing and packet switching technology, and provides a new design idea for chip interconnection. In addition to computing and storage resources in traditional SoC chips, network resources dedicated to data communication are introduced. The network on chip adopts the network structure of scalable parallel comm...

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Application Information

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IPC IPC(8): H04L45/023H04L45/121H04L45/125
CPCH04L45/023H04L45/121H04L45/125Y02D30/50
Inventor 郭汝佳徐长卿刘毅杨银堂
Owner XIDIAN UNIV
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