Low-power-consumption adaptive routing method in network on chip

Abstract

The present invention relates to the field of on-chip network technology, and discloses a low-power adaptive routing method in an on-chip network, including the following steps: S1. Calculate the distance between the source node and the destination node of the message in the two directions of x-dimension and y-dimension, if If the sum of the distances is zero, the routing is completed, otherwise step S2 is executed; S2, the network is divided into two virtual subnets x+y* and x-y*; S3, the message enters the virtual subnet x+y* or x-y* for routing . The present invention divides the physical network into two virtual subnets x+y* and x-y*, and the virtual subnets x+y* and x-y* all adopt the complete adaptive routing algorithm of the shortest path and the new EVC flow control technology, According to the offset value of the destination node of the data packet relative to the source node, it is injected into the corresponding virtual network, and adaptively routed to the destination in the virtual network. The EVC channel is used first when the data packet is routed, and the NVC channel is used only when there is no free EVC channel available. It proceeds according to the normal pipeline stage, which effectively improves performance and reduces power consumption.

Description

technical field [0001] The invention relates to the technical field of on-chip networks, in particular to a low-power adaptive routing method in on-chip networks. Background technique [0002] Due to the ever-increasing demand for communication bandwidth between multi-cores on a chip, the concept of Network on Chips (NoC) was proposed to specifically study and deal with communication problems between on-chip components such as multi-cores. In the field of network-on-chip, in addition to the bandwidth issue affecting performance, power consumption is also a key factor affecting the design of network-on-chip. Power consumption is mainly due to the movement of data in the network. Higher bandwidth will inevitably generate more power consumption. Therefore, how to balance the two conflicting factors of bandwidth and power consumption is crucial to the design of high-performance on-chip networks. important. Constructing a system-level power consumption model and proposing a low...

AI Technical Summary

Problems solved by technology

The ORION power consumption estimation model can only estimate the overall energy consumption of the on-chip network, and lacks a mechanism to measure the peak power consumption of the on-chip network during actual operation

Images