Semiconductor packaging method and semiconductor packaging structure

A packaging method and packaging structure technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem of large stress difference between rewiring layer and insulating layer layer, affecting the normal operation of the product, etc., to reduce the risk of warpage, improve quality, and achieve the effect of free thickness design

Pending Publication Date: 2022-01-28
SIPLP MICROELECTRONICS CHONGQING CO LTD
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  • Abstract
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  • Application Information

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Problems solved by technology

Due to the large difference in thermal expansion coefficient between the rewiring layer and the insulating layer, the temperature rise of the rewiring layer during the preparation or chip operation will cause a large stress difference between the rewiring layer and the insulating layer, which may cause the rewiring layer and the insulating layer Delamination of layers or warping of rewiring layers will affect the normal operation of the product

Method used

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  • Semiconductor packaging method and semiconductor packaging structure
  • Semiconductor packaging method and semiconductor packaging structure
  • Semiconductor packaging method and semiconductor packaging structure

Examples

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Embodiment Construction

[0048] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application as recited in the appended claims.

[0049] The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term ...

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Abstract

The invention provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: forming an encapsulation structure, wherein the encapsulation structure comprises an encapsulation layer and a chip, a plurality of welding pads are arranged on the front surface of the chip, and the encapsulation layer at least covers the side surface of the chip; forming a rewiring layer on one side, close to the front surface of the chip, of the packaging structure, wherein the rewiring layer leads out the welding pads of the chip; forming a dielectric layer, wherein the dielectric layer covers the rewiring layer, and a through hole for exposing the rewiring layer is formed in the dielectric layer; and forming a pin layer on one side, deviating from the chip, of the dielectric layer, wherein the pin layer is electrically connected with the rewiring layer through the through hole.

Description

technical field [0001] The present application relates to the field of semiconductor technology, in particular to a semiconductor packaging method and a semiconductor packaging structure. Background technique [0002] Common semiconductor packaging technologies, such as chip packaging technology, mainly include the following process: For the process of processing the front side of the chip, first mount the front side of the chip on the carrier board, perform thermocompression molding, peel off the carrier board, and then A rewiring layer and a pin layer located on the side of the rewiring layer away from the chip are formed on the front side of the chip, and then an insulating layer is formed, the insulating layer covers the rewiring layer, and the insulating layer is exposed on the surface of the pin layer away from the chip. [0003] In the existing chip packaging technology, since the pin layer is formed on the side of the rewiring layer away from the chip, the area of ​​...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L21/56H01L23/49H01L23/498H01L23/31
CPCH01L21/4885H01L21/4889H01L21/4846H01L21/4853H01L21/56H01L23/49H01L23/49811H01L23/49838H01L23/3114H01L2224/18H01L21/568H01L24/08H01L23/3107H01L24/03H01L24/05H01L24/11H01L24/13H01L2224/03013H01L2224/033H01L2224/0401H01L2224/1147H01L2224/13007H01L2224/13082
Inventor 霍炎涂旭峰
Owner SIPLP MICROELECTRONICS CHONGQING CO LTD
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