SiC MOSFET device integrating groove and body plane gate

A planar gate and trench technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as device reliability degradation, achieve the effects of improving robustness, improving device switching performance, and reducing device gate charge

Pending Publication Date: 2021-11-09
CHONGQING UNIV OF POSTS & TELECOMM
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This makes it easier for the gate oxide layer at the corner of the trench gate of the SiC trench MOSFET device to break down first, causing a decrease in the reliability of the device

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SiC MOSFET device integrating groove and body plane gate
  • SiC MOSFET device integrating groove and body plane gate
  • SiC MOSFET device integrating groove and body plane gate

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0049] Such as figure 1 and figure 2 As shown, the structure of the present invention compared with the traditional trench gate MOSFET is as follows, including drain metal contact region 1, N+ substrate 2, N-drift region 3, P-body region 4, P+ source region 5, N+ source region 6, source Metal 7, insulating dielectric layer 8, P+ polysilicon 10, gate metal contact region 11.

[0050] The drain metal contact region 1 is located on the lower surface of the N+ substrate layer 2 .

[0051] The N+ substrate layer 2 is located on the lower surface of the N-drift region 3 and the upper surface of the drain metal contact region 1; the length in the horizontal direction is 4 μm, and the length in the vertical direction is 3 μm; the doped N-type impurity concentration is 2×10 19 cm -3 .

[0052] The N-drift region 3 is located on the lower surface of the P-body region 4, the lower surface and the outer lower surface of the insulating dielectric layer 8, and is also located on the up...

Embodiment 2

[0061] Such as image 3 and Figure 4 As shown, the present invention relates to a SiC MOSFET device structure of an improved SiC MOSFET device integrating a trench gate and a body planar gate. The device includes a drain metal contact region 1, an N+ substrate 2, an N-drift region 3, a P- Body region 4, P+ source region 5, N+ source region 6, source metal 7, insulating dielectric layer 8, P+ polysilicon 10, gate metal contact region 10, gate bottom channel region 11, gate bottom N+ source region 12, gate bottom P electric field shielding region 13 , current spreading region 14 , and second drift region 15 .

[0062] The drain metal contact region 1 is located on the lower surface of the N+ substrate 2 .

[0063] The N+ substrate layer 2 is respectively located on the lower surface of the N- drift region 3 and the upper surface of the cathode metal contact region 1; the length in the horizontal direction is 4 μm, and the length in the vertical direction is 3 μm; the doped N-...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Side wall thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to view more

Abstract

The invention relates to a SiC MOSFET device integrated with a groove and a body plane gate, and belongs to the technical field of semiconductors. According to the MOSFET, on the basis of a traditional trench gate, a body plane gate structure is introduced into the bottom of the trench gate. The body plane gate is composed of source metal, a gate insulating dielectric layer, a gate bottom N+ source, a gate bottom P electric field shielding region and a gate bottom channel region, and the gate bottom N+ source and the gate bottom P electric field shielding region are in short circuit with the source metal. The body plane gate not only introduces a new channel, but also integrates a new PN junction diode between a P electric field shielding region and an N-drift region. Compared with a traditional groove type SiC MOSFET, the groove gate bottom peak electric field is reduced by 75.3%; the gate-drain charge is reduced by 91.5%; the starting loss is reduced by 66.6% at the frequency of 1MHZ; and the turn-off loss is reduced by 78.0%.

Description

technical field [0001] The invention belongs to the technical field of semiconductors and relates to a SiC MOSFET device integrating trenches and body plane gates. Background technique [0002] SiC (silicon carbide) is a compound semiconductor material composed of silicon (Si) and carbon (C). The advantage of SiC is not only that its insulation breakdown field strength is 10 times that of Si, and its band gap is 3 times that of Si, but also that it can achieve the necessary P-type and N-type control in a wide range during device manufacturing, so it is considered It is a material used to manufacture power devices that exceeds the limit of Si. SiC material can achieve high voltage with majority-carrier devices (Schottky barrier diodes and MOSFETs) with fast device structure characteristics, so "high withstand voltage", "low on-resistance", and "high frequency" can be realized at the same time these three characteristics. The drift layer resistance of SiC devices is smaller...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L29/16H01L29/423H01L29/78
CPCH01L29/1608H01L29/42356H01L29/4236H01L29/7827H01L29/7831
Inventor 陈伟中许峰秦海峰王玉婵
Owner CHONGQING UNIV OF POSTS & TELECOMM
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap