Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the steps that: an initial substrate is provided, wherein the initial substrate comprises a first sacrificial film, a first channel film, a second sacrificial film, a second channel film and a third sacrificial film which are sequentially stacked from bottom to top; the third sacrificial film and the second channel film are etched until the surface of the second sacrificial film is exposed to form a third sacrificial layer and a second channel layer; a first protection layer is formed on the side wall of the second channel layer; the second sacrificial film and the first channel film are etched until the surface of the first sacrificial film is exposed to form a second sacrificial layer and a first channel layer; a second protection layer is formed on the side wall of the second channel layer, the side wall of the second sacrificial layer and the side wall of the first channel layer; and the first sacrificial film and a part of the initial substrate are etched to enable the first sacrificial film to form a first sacrificial layer. According to the semiconductor structure and the forming method thereof disclosed by the invention, the CFET manufacturing process is improved, and the performance of the semiconductor structure is improved.

Description

technical field [0001] The present application relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a method for forming the same. Background technique [0002] The gate of a traditional FinFET (Fin Field Effect Transistor) only surrounds the channel region on three sides, and the bottom of the gate is connected to the semiconductor substrate, which may cause leakage current when the FinFET is turned off. For this reason, a kind of Complementary Field Effect Transistor (CFET, Complementary Field Effect Transistor) is proposed in the prior art, which adopts the gate surround technology, and the channels of the n-type field effect transistor and the p-type field effect transistor in the sheet form The regions are stacked one above the other and the gate completely surrounds the channel region, which not only effectively solves the problem of leakage current, but also reduces the size of the transistor by nearly one-third. [0003...

AI Technical Summary

Problems solved by technology

[0005] This application aims to solve the technical problems of narrowing of the sacrificial layer, non-uniform trench depth and / or insufficient remaining thickness of the hard mask layer during the fabrication of CFETs

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