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FPGA layout and wiring method with soft error sensing

A technology of placement and routing, soft error, applied in the field of FPGA placement and routing of soft error perception, can solve problems such as prominent irradiation problem, and achieve the effect of solving low operation efficiency, improving parallelism, and improving robustness

Pending Publication Date: 2021-10-15
BEIJING MXTRONICS CORP +1
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  • Application Information

AI Technical Summary

Problems solved by technology

However, with the large-scale use of FPGA, the radiation problem in space applications is becoming more and more prominent

Method used

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  • FPGA layout and wiring method with soft error sensing
  • FPGA layout and wiring method with soft error sensing
  • FPGA layout and wiring method with soft error sensing

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Embodiment Construction

[0048] The present invention will be further elaborated below in conjunction with embodiment.

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0050] The idea of ​​the present invention is as figure 1 As shown: Step S1, firstly, analyze and model the soft errors caused by the single event effect in the routing resources in the FPGA; Step S2, introduce the radiation-resistant layout factor in the FPGA layout process, and define the radiation-resistant layout cost function, here On the basis of using the me...

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Abstract

The invention relates to an FPGA layout and wiring method with soft error sensing. The method comprises the following steps: firstly, finishing analysis and modeling of soft errors of wiring resources in an FPGA; on the basis of research on a soft error model, introducing an anti-radiation factor in the layout and wiring process, and improving the soft error sensing capacity of the layout and wiring method; aiming at the problem of slow convergence caused by a random process and iteration in the layout process, optimizing the layout process by using a direct process enhanced learning method, so that the layout process is more intelligent and efficient; in order to solve the problem that the wiring speed is low, carrying out recursive division on wire nets with different characteristics on the basis of a novel rewiring strategy, and then adopting different parallel wiring strategies to complete the parallel wiring process. The layout and wiring method has a soft error sensing capability, can relieve the influence on the circuit performance caused by soft errors of wiring resources in the FPGA, and can reduce the system compiling time on the basis of increasing the intelligent degree of the system.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a soft-error-aware FPGA layout and wiring method. Background technique [0002] SRAM-type FPGA has the advantages of reprogrammable, high density, low power consumption, fast speed, etc., and has been widely used once it comes out. In the electronic systems of various important core fields such as military weaponry, aviation, aerospace, weapons, ships, etc., FPGA is playing a role that other chips cannot replace. However, with the large-scale use of FPGA, the radiation problem in space applications is becoming more and more prominent. There are a large number of high-energy particles in the universe, and these high-energy particles will affect the functions of SRAM FPGA electronic devices and cause soft errors. Therefore, it is particularly important to conduct research on anti-radiation mitigation strategies for SRAM FPGAs and to prolong the service life of SRAM FPGAs and ae...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/394G06F30/398
CPCG06F30/394G06F30/398
Inventor 田春生陈雷王硕周婧庞永江周冲马筱婧张瑶伟杜忠张璐席培培王郁景
Owner BEIJING MXTRONICS CORP
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