Full adder function implementation method based on resistive device

Abstract

The invention discloses a full adder function implementation method based on a resistive device. The method comprises the steps: adopting five memristors, setting two resistance states of the memristors according to resistance values of the memristors, and defining the initialized logic parameters of the memristors, input and output of the memristors and output of the memristors after read-write operation; adopting a semiconductor parameter analysis tester to apply positive scanning voltage and negative scanning voltage to the memristor to obtain threshold voltage of resistance state conversion of the memristor, and determining the amplitude of pulse voltage with the pulse width of 50 microseconds input by the memristor based on the threshold voltage; then initializing each memristor to a corresponding resistance state according to a full adder function to be realized, and then performing corresponding write operation on the memristors, so the binary one-bit full adder function can be realized. The method has the advantages of simplifying the operation method, greatly reducing the number of devices, reducing the circuit area and reducing the circuit power consumption.

Description

technical field [0001] The invention relates to a method for realizing a full adder function, in particular to a method for realizing a full adder function based on a resistive variable device. Background technique [0002] Traditional CMOS full adders mainly include modules such as AND gates, OR gates, and XOR gates. The traditional CMOS full adder implements addition operations and is often used as a computer arithmetic logic unit to perform logic operations, shifts, and instruction calls. Memristors are characterized by their small size, multi-resistance, low power consumption, and non-volatility. At present, the implementation of the full adder function is mainly based on CMOS devices. As the value of the two addition numbers increases, the number of adders increases, and the defects of the adder itself such as large delay and high power consumption become increasingly prominent, and the improvement of CMOS transistor devices is slow. Shrinkage is slowing down, and man...

AI Technical Summary

Problems solved by technology

At present, the implementation of the full adder function is mainly based on CMOS devices. As the value of the two addition numbers increases, the number of adders increases, and the defects of the adder itself such as large delay and high power consumption become increasingly prominent, and the improvement of CMOS transistor devices is slow. Shrinkage slows down, manufacturing processes are facing physical limits

Therefore, the CMOS adder has problems such as large power consumption, large delay, and large area in the process of processing data.

Images