Interlayer dielectric cavity fault test structure and test method based on switched capacitor

A technology for interlayer dielectric and fault testing, applied in electronic circuit testing, measuring electricity, measuring devices, etc., can solve the problems of detection accuracy restriction and inapplicability, and achieve the effect of improving process and high testing accuracy.

Pending Publication Date: 2021-10-01
HARBIN INST OF TECH
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problem that the interlayer dielectric void fault of the existing M3D integrated circuit is detected by a microscope, the detection accuracy is restricted by various conditions and is not suitable for large-scale chip testing. The present invention provides an interlayer dielectric void fault based on switched capacitors Test structure and test method

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  • Interlayer dielectric cavity fault test structure and test method based on switched capacitor
  • Interlayer dielectric cavity fault test structure and test method based on switched capacitor
  • Interlayer dielectric cavity fault test structure and test method based on switched capacitor

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specific Embodiment approach 1

[0051] Specific implementation mode 1. Combination figure 1 As shown, the first aspect of the present invention provides a kind of interlayer dielectric void failure test structure based on switched capacitance, including CP control unit 100 and a plurality of test units 200;

[0052] Each test unit 200 includes a test capacitor and four transmission gate switches,

[0053] The CP control unit 100 is used to control the opening and closing of the four transmission gate switches in each test unit 200;

[0054] One end of the No. 1 transmission gate switch is connected to the power supply VD, and the other end is connected to the test input terminals of all the logic gates to be tested on the integrated circuit; one end of the No. 3 transmission gate switch is grounded, and the other end is connected to the test input terminals of all the logic gates to be tested; One end of the No. 4 transmission gate switch is connected to the test input terminals of all the logic gates to be...

specific Embodiment approach 2

[0060] Specific embodiment two, combine Figure 1 to Figure 5 As shown, another aspect of the present invention also provides a method for testing interlayer dielectric void failure based on switched capacitors, which is implemented based on the structure for testing interlayer dielectric void faults based on switched capacitors described in the first specific embodiment,

[0061] Each test unit 200 realizes the same method for void fault testing;

[0062] The interlayer dielectric test structure involved in the method of the present invention is as figure 1 shown. Each test unit is responsible for monitoring the N logic gates on the upper layer of the ILD. A test unit contains a voltage of V D The DC power supply (V D The value is determined by the power supply voltage of the MOS tube), four transmission gate switches TG and a test capacitor with known capacitance value (the capacitance value of the test capacitor is C eq0 1000 times). The on and off of each transmission...

specific Embodiment

[0114] For the use of 22nm process, interlayer dielectric thickness T ILD For a 20nm M3D integrated circuit, the simulation process and derivation results of void fault detection are introduced in detail. The process parameters of the transistors inside the M3D integrated circuit are: T ox = 1 nm, T Si =6nm, W=300nm, L=22nm.

[0115] First, determine the quantity N=200 of a group of logic gates that can be monitored by a test unit 200, and calculate the equivalent capacitance value C of a group of logic gates on the ILD upper layer when there is no void fault eq0 . Taking the NAND gate as an example, the number of MOS transistors included in a logic gate is m=4. When there is no void fault inside the interlayer medium, according to C eq0 The solution formula can determine the equivalent capacitance C of the logic gate eq0 =7.935fF.

[0116] Second, determine the switch equivalent capacitance C S and the number of switching times n when there is no fault 0 . Build the...

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Abstract

The invention discloses an interlayer dielectric cavity fault test structure and method based on a switched capacitor, and belongs to the field of high-density integrated circuit testing. The method aims at solving the problems that interlayer dielectric cavity fault detection precision is low and the method is not suitable for large-scale chip testing. The test structure comprises a CP control unit and a test unit. The test unit comprises a test capacitor and four transmission gate switches, and the CP control unit controls on and off of the four transmission gate switches in the test unit; one end of the first transmission gate switch is connected with the power supply VD, and the other end is connected with a test input end of a to-be-tested logic gate on the integrated circuit; one end of the third transmission gate switch is grounded, and the other end is connected with the test input end of the to-be-tested logic gate; one end of the second transmission gate switch is connected with the test input end of the to-be-tested logic gate, and the other end is connected with one end of the test capacitor, and the other end of the test capacitor is grounded; and one end of the fourth transmission gate switch is connected with one end of the test capacitor, and the other end of the fourth transmission gate switch is grounded. The structure and the method are used for medium cavity fault testing.

Description

technical field [0001] The invention relates to an interlayer dielectric void fault testing structure and testing method based on switched capacitors, and belongs to the field of high-density integrated circuit testing. Background technique [0002] Today, 3D integrated circuits based on through-silicon vias have become the main solution beyond Moore's Law with their superior electrical properties. However, the volume of TSVs and the high requirements for wafer alignment accuracy limit the integration of devices. Currently, monolithic three-dimensional integrated circuits (Monolithic Three-dimensional Integrated Circuits, M3D ICs) are receiving extensive attention. Compared with TSV-based 3D integrated circuits, monolithic 3D integrated circuits can significantly reduce chip area and improve circuit performance. However, the high integration density and the substantial reduction in the thickness of the interlayer dielectric make M3D integrated circuits extremely prone to i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2853
Inventor 杨智明俞洋肖紫文方旭
Owner HARBIN INST OF TECH
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