Formation method of semiconductor device

Abstract

The invention discloses a formation method of a semiconductor device, wherein the method comprises the steps: providing a device layout, and respectively scanning source and drain plug groove patterns in a threshold region around each initial gate plug groove pattern so as to obtain a density parameter of each initial gate plug groove pattern; according to the density parameter, each initial gate plug groove pattern is compensated to obtain a gate plug groove correction pattern, and the feature size of the gate plug groove correction pattern is reduced along with the increase of the density parameter; and a flat layer and a dielectric layer are etched to form a gate plug groove. By adopting the scheme, the rates of etching the dielectric layer and the flat layer are relatively low in the region with relatively high density of the source and drain plug groove, so that the problem of over-etching when the gate plug groove is formed by etching is avoided. In the region with the small density of the source and drain plug groove, the rate of etching the dielectric layer and the flat layer is large, and the problem that etching is insufficient when the gate plug groove is formed through etching is avoided. Therefore, the morphology of the finally formed gate plug groove is more uniform.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] In the semiconductor manufacturing process, it is a very important and complicated process to transfer the pattern on the mask to the semiconductor chip through the steps of photolithography and etching. [0003] The size of a specific pattern after photolithography is characterized by the after develop inspection critical dimension (ADI CD), and the size of the ADI CD directly affects the after Etch inspection critical dimension (AEI CD) . Before etching, it is necessary to deposit a dielectric layer and a planar layer, and form a patterned photoresist layer on the planar layer, and then use the patterned photoresist layer to etch the planar layer and then the dielectric layer. [0004] The density of the source-drain plug grooves formed in the dielectric layer under the flat layer is different, ...

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Problems solved by technology

[0006] The purpose of the present invention is to solve the problem of over-etching or under-etching in the prior art when forming gate plug grooves, which affects the performance of semiconductor devices.

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