Wafer assembly

A technology of wafers and components, applied in the direction of electrical components, electrical solid devices, semiconductor devices, etc., can solve problems affecting the efficiency and accuracy of wafer bonding recognition, small pattern size, etc., to improve recognition efficiency and accuracy, improve key Combined precision, the effect of large chip effective area

Pending Publication Date: 2021-09-21
WUHAN XINXIN SEMICON MFG CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the width of the 3D-IC design dicing line becomes smaller and smaller, the pattern size for the alignment mark is bound to become smaller and smaller, which affects the efficiency and accuracy of wafer bonding recognition

Method used

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Embodiment Construction

[0033] As mentioned in the background art, as the width of dicing lines in 3D-IC design becomes smaller and smaller, the size of the patterns left for alignment marks is bound to become smaller, which affects the efficiency and accuracy of wafer bonding recognition. Specifically, such as figure 1 As shown, the wafer assembly includes two wafers, one wafer includes an alignment mark 01, and the other wafer includes an alignment mark 02, and the alignment mark 01 and the alignment mark 02 are matched for the pairing of the two wafers. allow. The line width of the alignment mark 01 is b, the line width of the alignment mark 02 is a, and the line length of the alignment mark 02 is c. The width d of the scribe line S itself is getting smaller and smaller. The line width a of the alignment mark 02 plus the line width b of the alignment mark 01 plus the line length c of the alignment mark 02 must be smaller than the width d of the scribe line, that is, a+ b+c<d. In this way, the w...

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PUM

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Abstract

The invention provides a wafer assembly. The wafer assembly comprises a first wafer and a first alignment mark located on the first wafer, a second wafer and a second alignment mark located on the second wafer. At least one of the first alignment mark and the second alignment mark extends from an intersection area of the cutting channels to a non-intersection area on the wafer where the first alignment mark and the second alignment mark are located. The length of a pattern (such as a strip-shaped pattern) in the first alignment mark and / or the second alignment mark can be larger than the width of the cutting channel and is not limited by the width of the cutting channel any more. On the basis of an existing wafer bonding machine and process conditions, large-size alignment marks can be made under the condition that the width of a cutting channel is fixed, and the wafer bonding recognition efficiency and precision are improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a wafer component. Background technique [0002] In integrated circuit technology, three-dimensional integration (3D-IC) is a solution to improve chip performance while maintaining existing technology nodes. The performance of the chip can be improved by three-dimensional integration of two or more chips with the same or different functions. At the same time, the metal interconnection between functional chips can be greatly shortened, and heat generation, power consumption and delay can be reduced. In 3D-IC technology, the bonding process between wafers is a very critical technology. The quality of the bonding process between two wafers determines the success of the entire process. Among them, for bonding Alignment marks play a crucial role in the process. Among them, the recognition efficiency of the alignment mark is the core focus of the ...

Claims

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Application Information

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IPC IPC(8): H01L23/544H01L25/065H01L25/18
CPCH01L23/544H01L25/0657H01L25/18H01L2223/54426
Inventor 吴星鑫
Owner WUHAN XINXIN SEMICON MFG CO LTD
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