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FPGA acceleration implementation method based on unilateral Jacobian singular value decomposition

A technology of singular value decomposition and implementation method, applied in the field of FPGA acceleration implementation based on unilateral Jacobian singular value decomposition, can solve problems such as not mentioned, achieve simplifying complex design, improve FPGA routing rate and clock operating frequency, The effect of reducing consumption

Active Publication Date: 2021-06-01
ZHEJIANG LAB
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

This method requires the input matrix to be a real symmetric covariance matrix, and does not mention the difficulties faced by the singular value decomposition of large-scale matrices

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  • FPGA acceleration implementation method based on unilateral Jacobian singular value decomposition
  • FPGA acceleration implementation method based on unilateral Jacobian singular value decomposition
  • FPGA acceleration implementation method based on unilateral Jacobian singular value decomposition

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Embodiment Construction

[0035] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the purpose and effect of the present invention will become clearer. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

[0036] Some technical terms are used in the present invention, and explanations are given here:

[0037] (1) FPGA: Field Programmable Gate Array Field Programmable Gate Array

[0038] (2) BRAM: Block RAM, FPGA internal block RAM

[0039] (3) Jacobi: In this invention, it refers specifically to unilateral Jacobi rotation, which is often used in FPGA-based matrix singular value decomposition

[0040] (4) round-robin: Round-robin scheduling, a commonly used scheduling mechanism for unilateral Jacobi rotation singular value decomposition;

[0041] (5) CORDIC: Coordinate Rotation Digital Computer, coordinate ...

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Abstract

The invention discloses an FPGA accelerated implementation method based on unilateral Jacobian singular value decomposition. The method first divides the input matrix into n / 2 pairs of column vectors on average, and calculates the norm and inner product of each pair of column vectors, and then calculates The rotation matrix of each pair of column vectors, and perform orthogonal transformation, and then use the round-robin scheduling mechanism to write the column vectors obtained after performing the orthogonal transformation into the corresponding adjacent column vectors for replacement, so as to realize each round of unilateral Jacobi Calculations are performed on the same circuit for cyclic iterations, which simplifies the complex design of data channels and control channels, avoids the use of massive signal routing resources in the FPGA implementation process, reduces FPGA resource consumption, and improves circuit working clock frequency, thereby significantly improving overall performance.

Description

technical field [0001] The invention relates to the field of signal processing, in particular to an FPGA acceleration implementation method based on unilateral Jacobian singular value decomposition. Background technique [0002] Singular value decomposition is a bright spot in linear algebra, plays an important role in matrix decomposition, and is widely used in millimeter wave radar, wireless communication, image compression and deep learning and other fields. In the existing researches, the implementation mainly adopts CPU or GPU in the way of software program. The FPGA-based Jacobi algorithm realizes the singular value decomposition of the matrix. Although it combines the advantages of high parallel properties shared by both the FPGA and the Jacobi algorithm, the singular value decomposition of the matrix involves read and write access of row and column elements, frequent data scheduling replacement, A large number of loop iterations still have great difficulties in FPGA...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/57G06F17/16
CPCG06F7/57G06F17/16
Inventor 胡塘卢昊
Owner ZHEJIANG LAB
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