Multi-core tensor processor of neural network

A neural network and processor technology, applied in the field of artificial intelligence chips, can solve the problems of unfavorable computing efficiency, not widely used, redundant instructions, etc., to achieve the effect of improving computing efficiency

Active Publication Date: 2021-03-30
厦门壹普智慧科技有限公司
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 3) MISD (Multiple Instruction Single Data): Multiple instructions process one data, which is not commonly used at present
[0018] Since artificial intelligence computing tasks are data-intensive tasks, the instruction pipeline architecture of traditional processors will introduce too much instruction redundancy, which is not conducive to the improvement of computing efficiency

Method used

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  • Multi-core tensor processor of neural network
  • Multi-core tensor processor of neural network
  • Multi-core tensor processor of neural network

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Embodiment 1

[0048] Such as figure 1 As shown, the technical solution of this embodiment is to provide a hardware architecture of a neural network multi-core tensor processor, figure 1 shown. It is mainly composed of three parts: Host Controller, Reconfiguration Controller and multiple Data-flow Computing Engines.

[0049] In order to improve the flexibility of system integration, the tensor processor adopts the asynchronous clock scheme between the system core and the AXI bus interface. The system uses four completely independent asynchronous clocks to realize the isolation between the tensor processor core and the external system. Among them, the AXI slave device interface uses one AXI slave device bus clock (slave clk), the AXI master device interface uses two AXI master device bus clocks (master0 clk and master1 clk), and the tensor processor core uses the core clock (coreclk).

[0050] The role of the main controller is to provide external control and status interfaces, so that ext...

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Abstract

The invention discloses a multi-core tensor processor of a neural network. The multi-core tensor processor comprises a main controller, a reconstruction controller and a plurality of data flow calculation engines, the main controller is used for providing a control and state interface of the neural network tensor processor for an external control unit, and providing first configuration informationand a first initial signal for the reconstruction controller; the reconstruction controller receives the first configuration information and the first starting signal, obtains a reconstruction instruction of an external memory after the first starting signal is valid, and analyzes the reconstruction instruction to generate multiple groups of second configuration information and second starting signals; and each data flow calculation engine respectively receives the corresponding second configuration information and the second initial signal, performs function configuration according to the second configuration information, acquires data and parameters of the external memory to execute operation after the second initial signal is valid, and writes a calculation result into the external memory. The multi-core tensor processor is suitable for performing centralized calculation on a neural network algorithm, and has universality and expandability.

Description

technical field [0001] The invention relates to the technical field of artificial intelligence chips, in particular to a neural network multi-core tensor processor. Background technique [0002] Processor technology is one of the major manifestations of human technological progress. However, the abstract model of a processor is quite simple: (1) a processor consists of memory, I / O interfaces, a control unit, and a computing unit; (2) a processor loop performs the following operations: "fetch instruction / data, execute instruction , Write data"; (3) The behavior of the processor is completely determined by instructions and data. No matter how complex the processor is, be it CPU, GPU or DSP, the above model applies to all. This processor abstract model is the famous "von Neumann structure", the core of which is to store the program used for control as data. This computing model based on the stored program has been used until now. However, the complexity of the device structu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/04
CPCG06N3/063G06N3/045Y02D10/00
Inventor 罗闳訚周志新何日辉
Owner 厦门壹普智慧科技有限公司
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