Low-delay parallel digital down-conversion method and system

A digital down-conversion and low-latency technology, applied in digital transmission systems, transmission systems, modulated carrier systems, etc., can solve problems such as resource consumption, increased delay, and performance impact

Active Publication Date: 2021-03-26
上海擎昆信息科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007]However, in order to achieve high-precision frequency offset compensation, the look-up table method needs to store a relatively large table, which takes up more resources; the digital calculation method of coordinate rotation will increase the delay , and in order to achieve higher precision, a large number of iterations is required, which will also increase power consumption; the second look-up table method is a compromise solution, which can better balance storage space and power consumption, but after the second look-up table method is still It is necessary to do one more complex multiplication, which will also consume certain resources, and the performance is also affected by the size of the secondary lookup table, so it is difficult to achieve high precision

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Embodiment 1

[0106] An embodiment of the present invention, such as figure 1 As shown, the present invention provides a low-latency parallel digital down-conversion method, comprising steps:

[0107] S1. Before the prompt signal (Refresh) of parameter change is refreshed, the intermediate frequency frequency and sampling rate are obtained, and the frequency offset compensation value and the initial phase of the current cycle are calculated in an eight-way parallel processing manner.

[0108] Specifically, before the prompt signal of parameter change is refreshed, the intermediate frequency frequency f0 and sampling rate fs are obtained, and the frequency offset compensation value fac and the initial phase phi of the current cycle are calculated according to the eight-way parallel processing method, fac=f0 / fs*2 ^32, phi=0.

[0109] For example, for a certain wireless communication receiver, fs=2.4G, the signal needs to be down-converted f0=300M, then fac=300 / 2400*2^32, phi=0.

[0110] S2....

Embodiment 2

[0141] An embodiment of the present invention, on the basis of Embodiment 1, after obtaining the frequency offset compensation value and the initial sine and cosine values ​​of the initial phase, further includes: storing the initial sine and cosine values.

[0142] After obtaining the calculation initial value, it also includes: storing the calculation initial value.

[0143] Specifically, cos(fac), sin(fac), cos(phi), sin(phi), cos(8*fac), and sin(8*fac) are stored in registers 1-6 respectively, and the initial calculation value is stored in Register 7. Certainly, various registers may also be combined. For example, in this embodiment, registers 1-4 are combined into one register, registers 5-6 are combined into one register, and register 7 is a single register.

[0144] Preferably, after obtaining the output waveform of the current calculation according to the refreshed initial calculation value, the method further includes: re-refreshing the stored initial calculation val...

Embodiment 3

[0150] An embodiment of the present invention, such as image 3 As shown, the present invention also provides a low-latency parallel digital down-conversion system, including a phase accumulator, a CORIDC calculator, a waveform generator, a serial-to-parallel converter, an eight-way parallel down-converter and a parallel-to-serial converter.

[0151] The phase accumulator 10 is used to obtain the intermediate frequency and sampling rate before the prompt signal of parameter change is refreshed, calculate the frequency offset compensation value according to eight-way parallel processing, and configure the initial phase of the current cycle.

[0152] Specifically, before the prompt signal (Refresh) of parameter change is refreshed, the intermediate frequency frequency f0 and the sampling rate fs are obtained, and the frequency offset compensation value fac and the initial phase phi of the current cycle are calculated according to the eight-way parallel processing method, fac=f0 / ...

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Abstract

The invention provides a low-delay parallel digital down-conversion method and system, and the method comprises the steps: obtaining an intermediate frequency and a sampling rate before a prompt signal with changed parameters is refreshed, and calculating a frequency offset compensation value and an initial phase of a current period in an eight-path parallel processing mode; performing iterative computation on the frequency offset compensation value and the initial phase through a coordinate rotation digital computation method to obtain waveform data; obtaining a calculation initial value according to the waveform data; when the prompt signal of the parameter change is refreshed, obtaining an output waveform of the current calculation according to the refreshed calculation initial value; performing eight-path parallel down-conversion on the input data subjected to serial-parallel conversion and the output waveform to obtain output data; and carrying out parallel-serial conversion on the output data and then outputting the output data. According to the scheme, fewer storage resources are required, the time delay is lower, and higher compensation precision can be realized.

Description

technical field [0001] The invention relates to the technical field of wireless communication, in particular to a low-delay parallel digital down-conversion method and system. Background technique [0002] In wireless communication systems, it is often necessary to compensate the frequency offset of the received signal, for example, the signal sampling rate is f s , the frequency offset to be compensated is f 0 , the received signal is X(K) (k=0,1...n), and the signal after frequency offset compensation is y(k) (x, y are complex numbers), then: [0003] y(k)=x(k)*(cos(f0 / fs*2*pi*(k-1))+1i*sin(f0 / fs*2*pi*(k-1))), where, k=1,2,3...n; [0004] Equivalently viewed as: y(k)=x(k)*(cos(delta)+1i*sin(delta)), where k=1,...n, and delta is between 0-2*pi. [0005] When eight channels are used in parallel, the mth channel (m=0,1,2...7) at time k: y_m(k)=x(8*k+m)*(cos(8*f0 / fs*2*pi* (k-1)+m*f0 / fs)+1i*sin(f8*0 / fs*2*pi*(k-1))+m*f0 / fs). [0006] In a broadband wireless system, when th...

Claims

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Application Information

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IPC IPC(8): H04L27/00H03D7/16
CPCH04L27/0014H03D7/165H04L2027/0026
Inventor 谭定富是元吉唐兵武传国
Owner 上海擎昆信息科技有限公司
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