Foreground time error correction circuit of multi-channel time domain interleaved data converter
A technology for interleaving data and correcting circuits, applied in analog/digital conversion calibration/testing, analog/digital conversion, code conversion, etc. performance degradation and other issues, to achieve the effect of reducing stability requirements, reducing output data rate, and reducing the probability of enabling
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[0090] The present invention aims at the difficulty of correcting the channel time error of the ultra-high-speed time-domain interleaving data converter with more than 10 channels, and provides a front-end error automatic correction circuit to compensate the channel time error generated by the converter during the process of tape-out and actual use. Matching, reducing error and spurious signal components, improving parameters such as spurious-free dynamic range and signal-to-noise ratio, and improving the overall performance of the data converter.
[0091] The overall block diagram of the circuit of the present invention is as figure 1 shown. The circuit includes a down-sampling channel data extraction circuit, a zero-crossing detection circuit, a pre-normalization circuit, a negative feedback integration circuit, a convergence detection circuit, and a first-order Taylor expansion correction circuit. Because the clock distribution in the ultra-high-speed multi-channel time-do...
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