Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention provides a semiconductor device manufacturing method and a semiconductor device, and the method comprises the steps: providing a semiconductor substrate, and forming a gate structure onthe semiconductor substrate; executing a lightly doped source-drain ion implantation process to form lightly doped source-drain regions in the semiconductor substrate on two sides of the gate structure; executing bag region ion implantation to form a bag type ion implantation region at the bottom of the lightly doped source-drain region; and executing source-drain ion implantation to form a source-drain region in the semiconductor substrate on two sides of the gate, the lightly doped source-drain region, the bag type ion implantation region and the source-drain region jointly forming a source-drain electrode with an inclined morphology below the gate structure. According to the manufacturing method of the semiconductor device, under the condition that the area of the semiconductor device is the same as that of the semiconductor device, higher current capacity (the current capacity of transmission line pulse testing) can be achieved, and therefore higher robustness is achieved comparedwith a conventional process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor device and the semiconductor device. Background technique [0002] GGNMOS (Gate Grounded NMOS) is a commonly used ESD protection device. A typical GGNMOS device is shown in FIG. In the well 101, a gate structure 103 is formed on the semiconductor substrate 100, and a source 104 and a drain 105 are also formed in the semiconductor substrate 100 on both sides of the gate structure 103, wherein the gate structure 103 and the source 104 Together with the lead-out terminal 106 of the substrate, it constitutes the anode of the GGNMOS device, and the drain 105 is separately drawn out as the cathode. Isolation structures 107 are provided between the lead-out terminal 106 of the substrate, the source 104 and the drain 105 . When an ESD surge occurs at the anode, the diode formed by the drain 105 and the P well 101 in the substrate is r...

AI Technical Summary

Problems solved by technology

However, in the process of forming the source and drain, in order to prevent the current from concentrating on the surface, the source and drain ion implantation including inclined ion implantation is adopted, and the formed source and drain have a relatively vertical shape under the gate structure to increase the conductivity. area, such as Figure 1B shown, making the current path at the bottom of the source and drain (as Figure 1B Shown in P2) is larger, larger than the current path of the source-drain surface (such as Figure 1B (shown in P1), which makes it easier for the current to concentrate on the surface during electrostatic discharge, and the overcurrent protection capability per unit area is low

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