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Data merging method, memory storage device and memory control circuit unit

A technology for controlling circuits and storage devices, which is applied in electrical digital data processing, input/output processes of data processing, instruments, etc., can solve the problems of increasing the number of accesses of memory storage devices, and reducing the overall performance of memory storage devices, etc. Overall operating performance, the effect of reducing the number of accesses

Pending Publication Date: 2021-02-23
PHISON ELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when there is a large amount of management information to be accessed, it will increase the access times of the memory storage device and cause the overall performance of the memory storage device to decrease

Method used

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  • Data merging method, memory storage device and memory control circuit unit
  • Data merging method, memory storage device and memory control circuit unit
  • Data merging method, memory storage device and memory control circuit unit

Examples

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Embodiment Construction

[0036] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts.

[0037] Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

[0038] figure 1 It is a schematic diagram showing a host system, a memory storage device and an input / output (I / O) device according to an exemplary embodiment of the present invention. figure 2 It is a schematic diagram showing a host system, a memory storage device and an I / O device according to another exemplary ...

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Abstract

The invention provides a data merging method, a memory storage device and a memory control circuit unit. The data merging method is used for a rewritable nonvolatile memory module comprising a plurality of entity units. The method comprises the steps of starting a first data merging operation, and selecting a first entity unit used for executing the first data merging operation and a second entityunit used for executing a second data merging operation from entity units; in the first data merging operation, reading first mapping information from the rewritable nonvolatile memory module, and copying first valid data collected from the first entity unit to a third entity unit according to the first mapping information; in the first data merging operation, identifying second valid data in a second entity unit according to the first mapping information; and starting the second data merging operation, and copying the second valid data collected from the second entity unit to a fourth entityunit.

Description

technical field [0001] The invention relates to a flash memory technology, in particular to a data integration method, a memory storage device and a memory control circuit unit. Background technique [0002] Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for building in the above-mentioned Examples of various portable multimedia devices. [0003] When the memory storage device leaves the factory, some of the physical units in the memory storage device will be configured as a plurality of idle physical units, so as to use the idle physical units to store new data. After being used for a period of time, the number of idle physical units in the memory storage device will graduall...

Claims

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Application Information

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IPC IPC(8): G06F3/06G06F13/16
CPCG06F3/0646G06F3/061G06F3/0679G06F13/1668Y02D10/00
Inventor 叶志刚
Owner PHISON ELECTRONICS
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