Full-pipeline SMS4 encryption and decryption method and system

Abstract

The invention discloses a full-pipeline SMS4 encryption and decryption method and system. The method is characterized by using full-pipeline processing architecture based on a Block RAM; connecting all operational circuits for carrying out the n key generation in a one-time encryption and decryption conversion process, and n encryption and decryption completely in series; caching multi-clock-period intermediate operation data through the Block RAM, and storing an S box lookup table and a fixed parameter lookup table, wherein the intermediate operation data comprises a ciphertext, an intermediate key, a round key and an encryption and decryption trigger; realizing plaintext and ciphertext continuous input processing through a full-pipeline processing architecture; and realizing the multi-clock period delay output of the intermediate operation data through the read-write time difference of the dual-port Block RAM. An SMS4 algorithm is realized by using the pipeline architecture, FPGA embedded Block RAM resources are fully utilized to realize multi-clock-period caching of a large amount of intermediate operation data and S-box lookup table storage in a plurality of round key generation units and encryption and decryption units, the resource consumption of configurable logic blocks is reduced to the maximum extent, and the information throughput rate is improved to the maximum extent.

Description

technical field [0001] The invention relates to the technical field of data encryption, in particular to a full-line SMS4 encryption and decryption method and system. Background technique [0002] The SMS4 algorithm is the first commercial block cipher standard officially announced in China, and it is also the block cipher algorithm recommended by China's wireless LAN security standards. The block length and key length of the algorithm are both 128 bits, and the encryption algorithm adopts 32-round unbalanced Feistel structure. SMS4 goes through 32 rounds of non-linear iterations and then adds a reverse sequence transformation. Only the decryption key is the reverse sequence of the encryption key, so that the decryption algorithm can be consistent with the encryption algorithm. [0003] The 128-bit initial plaintext is divided into four 32-bit words, expressed as (X 0 ,X 1 ,X 2 ,X 3 ), the ciphertext is divided into 4 words, expressed as (Y 0 ,Y 1 ,Y 2 ,Y 3 ). Supp...

AI Technical Summary

Problems solved by technology

Although the traditional serial processing architecture can save circuit resources, the biggest disadvantage is that the next set of plaintext or ciphertext cannot be received and processed before a set of plaintext or ciphertext is encrypted or decrypted, and the information throughput rate is low.

Analyzing the above-mentioned SMS4 algorithm, it can be seen that the FPGA realizes single-channel serial processing of SMS4 encryption and decryption transformation, and the delay clock is at least 10 2 order of magnitude, that is to say, if real-time processing is required, the resource consumption of the multi-channel serial processing architecture to realize SMS4 encryption transformation and decryption transformation is at least 100 times higher than that of the single-channel serial processing architecture, so the multi-channel serial processing architecture is only suitable for Simultaneously handle application scenarios where the number of plaintext / ciphertext groups is not high

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