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A kind of semiconductor die with sealing ring structure and its preparation method

A technology of semiconductor tubes and sealing rings, applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., to achieve excellent water vapor resistance and eliminate cutting stress

Active Publication Date: 2022-01-11
ZHANGJIAGANG SHANMU NEW MATERIAL TECH DEV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But there is still room for improvement in the current sealing ring structure

Method used

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  • A kind of semiconductor die with sealing ring structure and its preparation method

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preparation example Construction

[0031] This embodiment provides a method for preparing a semiconductor die with a sealing ring structure, comprising the following steps:

[0032] Such as figure 1 As shown, 1) a semiconductor wafer 1 is provided, and the semiconductor wafer 1 includes a dicing area 11, an integrated circuit area 12 and a seal ring area 13 between the dicing area 11 and the integrated circuit area 12. A trench 14 is formed in the sealing ring region 13 of the semiconductor wafer 1 .

[0033] Wherein, the semiconductor wafer 1 can specifically be a silicon substrate, a germanium substrate, a silicon germanium substrate or an SOI substrate, and the integrated circuit region 12 has devices such as field effect transistors, resistors, capacitors, inductors, and diodes, and the trench 14 Formed by wet etching or dry etching, the depth of the trench 14 is 800-2500 nanometers.

[0034] In a specific embodiment, a photoresist is coated on the semiconductor wafer 1, and a mask with an exposed part of...

Embodiment 1

[0062] Implementation 1: A method for preparing a semiconductor die with a sealing ring structure, comprising the following steps:

[0063] 1) A semiconductor wafer is provided, the semiconductor wafer includes a dicing area, an integrated circuit area, and a sealing ring area between the dicing area and the integrated circuit area, and the sealing ring of the semiconductor wafer is A trench is formed in the region.

[0064]2) Next, a mask is formed on the semiconductor wafer, and the mask only exposes the region where the groove is located, and then a solution containing metal nanoparticles is spin-coated on the semiconductor wafer to form a layer in the groove. A first metal nanoparticle layer is formed in the groove, and then the mask is removed.

[0065] 3) Then forming a first dielectric layer on the semiconductor wafer, and then forming a plurality of first through holes on the first dielectric layer, the plurality of first through holes are arranged at intervals and ex...

Embodiment 2

[0072] Implementation 2: In the step 1), the trench is formed by wet etching or dry etching, and the depth of the trench is 800-2500 nanometers.

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Abstract

The invention relates to a semiconductor die with a sealing ring structure and a manufacturing method thereof, comprising the following steps: forming a groove in a sealing ring region of a semiconductor wafer, forming a first metal nanoparticle layer in the groove, Next, on the semiconductor wafer, a first dielectric layer, a first metal pillar, a second metal nanoparticle layer, a second dielectric layer, a second metal pillar, a third metal nanoparticle layer, a third dielectric layer, and a second metal nanoparticle layer are sequentially formed. Three metal pillars, a fourth metal nanoparticle layer and a fourth dielectric layer, wherein the fourth dielectric layer completely covers the fourth metal nanoparticle layer.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a semiconductor die with a sealing ring structure and a preparation method thereof. Background technique [0002] During the manufacturing process of the semiconductor die, the periphery of the die needs to pass through a sealing ring structure to keep the inside of the chip in a sealed state. The traditional sealing ring structure generally adopts multi-layer metal layer stacking, usually a single sealing ring structure, double-layer sealing ring structure or triple-layer sealing ring structure, and the width of the metal is about 10-20 microns. The sealing ring is a continuous metal wire surrounding the outer ring of the chip. The circuit area inside the sealing ring can be protected from the influence of the external environment, prevent the chip from cracking, and ensure the stable performance of the semiconductor chip for a long time. But there is still room for impr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/00H01L23/16
CPCH01L23/562H01L23/16
Inventor 沈佳慧汤亚勇苏华
Owner ZHANGJIAGANG SHANMU NEW MATERIAL TECH DEV
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