Failure analysis sample preparation method and failure analysis sample

Abstract

The invention provides a failure analysis sample preparation method and a failure analysis sample. The preparation method comprises the following steps: providing a stacked packaging body to be analyzed, wherein a plurality of stacked bare chips is arranged in the stacked packaging body, each bare chip is provided with a front surface provided with a welding pad and a back surface opposite to thefront surface, the back surface of each bare chip is in contact with the front surface of the adjacent bare chip, and the welding pad of each bare chip is electrically connected with the welding pad of the adjacent bare chip; removing other bare chips on the back surface of a target bare chip, and stopping until the welding pads of the bare chips adjacent to the target bare chip are exposed; and electrically leading out the exposed welding pad to form a sample for failure analysis. The method has the advantages that the back surface of the target bare chip is removed, and the non-target bare chip welding pads are used as electric connection parts, so that the removal operation on the front surface of the target bare chip with a circuit device is avoided, the circuit device on the front surface is protected, the complete and damage-free target bare chip can be prepared, the sample preparation success rate is greatly improved, and the sample preparation difficulty is greatly reduced.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method for preparing a failure analysis sample and the failure analysis sample. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the feature size of semiconductor devices continues to decrease, while the degree of integration continues to increase. Usually, in order to obtain a large-capacity memory chip, it is necessary to stack and package multiple memory dies in the same chip, up to 16 at present. The more dies in a stacked package, the thinner each die needs to be thinned. For failure analysis, it is often necessary to obtain the target single faulty die from multiple stacked dies for dynamic hotspot (dynamic hotspot) analysis. For stacked packages, the processing of samples with thin single die is extremely difficult. [0003] Therefore, how to reduce the difficulty of sample preparation and improve the success r...

AI Technical Summary

Problems solved by technology

For failure analysis, it is often necessary to obtain a target single faulty die from multiple stacked dies for dynamic hotspot analysis, which requires that the taken out target die be intact and free of damage, and be able to perform a complete electrical test. For stacked packages, and single die thinner samples are extremely difficult to handle

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