Multi-phase multi-duty-ratio clock generation circuit

Abstract

The invention discloses a multi-phase multi-duty-ratio clock generation circuit, which comprises an input buffer module of which the input end receives an input signal and the output end is connectedwith the input end of a frequency divider; the frequency divider of which the output end is connected with the input ends of two primary inverters; the two primary inverters, wherein the output end ofthe first primary inverter is connected with the input ends of a first secondary inverter and a third secondary inverter and the input end of a first primary clock output inverter, and the output endof the second first primary inverter is connected with the input ends of a second secondary inverter and a fourth secondary inverter and the input end of the second primary clock output inverter; thefour secondary intervers, wherein the output end of each secondary inverter is connected with the input ends of the two tertiary inverters; eight tertiary inverters connected with four AND gates; andthe four AND gates, wherein the output ends of the eight tertiaryinverters are connected with the first to fourth secondary clock output inverters respectively; and four secondary clock output inverters. The circuit overcomes the defects of low signal frequency, narrow bandwidth and single duty ratio of a multi-phase clock generation circuit.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a clock generation circuit with multiple phases and multiple duty ratios. Background technique [0002] At present, the multi-phase clock generation circuit can use the fixed-phase clock signal to generate multiple frequency-divided signals with fixed phase difference and fixed duty cycle or their frequency-multiplied signals, which are often used as the front end of the interleaving circuit. The requirements are getting higher and higher, and the clock interleaving technology is an important way to improve the working speed of the circuit, so the generation of multi-phase clocks is particularly important. [0003] In the prior art, almost all multi-phase clock generation circuits are built using CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) devices, which generally can only generate clock signals with a constant duty cycle, a...

AI Technical Summary

Problems solved by technology

The disadvantage is that the operating frequency range is still limited, the bandwidth is still narrow, and the duty cycle is single

In the patent document "A 25% Duty Cycle Clock Signal Generation Circuit" (Application No. CN201610622753.5, Publication No. CN106257835A), Wu Jianhui et al. of Southeast University also disclosed a 25% duty ratio built by CMOS. The four-phase clock generation circuit uses the phase difference of the frequency divider signal to generate a four-phase clock. The advantage is that the principle is simple and the power consumption is low. The disadvantage is still that the CMOS device is used, the clock bandwidth is limited, the maximum operating frequency is low and the duty cycle is low. single than the output state

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