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Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method

A self-alignment process and device structure technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of unsatisfactory ohmic contact resistance and demanding lithographic size requirements, and achieve epitaxial cost saving and balance Material damage, the effect of ensuring material quality

Active Publication Date: 2020-07-14
ZHEJIANG UNIV
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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a gallium nitride device structure combined with secondary epitaxy and self-alignment process and its preparation method, which is used to solve the problem of unsatisfactory ohmic contact resistance in the prior art. And lithography size requirements and other issues

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  • Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method

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[0073] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth sho...

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Abstract

The invention provides a gallium nitride device structure combining secondary epitaxy and a self-alignment process and a preparation method. The preparation method comprises the steps of: providing asemiconductor substrate; forming an epitaxial structure comprising a gallium nitride layer; forming a source structure and a drain structure through epitaxial growth under mask layer protection; forming a grid side wall; and forming a grid structure. According to the preparation method of the invention, the source electrode structure and the drain electrode structure are formed through secondary epitaxial growth, and therefore, ohmic contact resistance can be effectively reduced; the etching rate and material damage caused by etching are balanced through multi-step ion etching, oxidation and acid solvent digital etching before the secondary epitaxy, and process cost is considered while material quality is guaranteed; the self-alignment technology is adopted, errors caused by an alignment process in a photoetching process are avoided, and the size of a grid electrode is accurately defined; and the size of the grid electrode is controlled by utilizing the thickness of an isolation side wall, so that a grid pin photoetching step is omitted, and a technological process is simplified. With the preparation method adopted, the heteroepitaxy of GaN materials can be achieved on a large-sizewafer, and epitaxy cost per unit size is saved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a gallium nitride device structure combined with secondary epitaxy and self-alignment technology and a preparation method thereof. Background technique [0002] At present, the ohmic contact resistance obtained in the preparation of some semiconductor device structures is not ideal. For example, the ohmic contact resistance obtained in the existing GaNHEMT (High Electron Mobility Transistor) device is not ideal. In addition, in the device manufacturing process, ion implantation technology requires subsequent high-temperature annealing treatment to activate the implanted ions, and at the same time restore the material lattice damage caused by ion implantation, which will damage the material, and the ion activation rate is not high enough, so the ohm Contact resistance has always restricted the development of GaN devices to higher frequencies. ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/778H01L21/335H01L29/417H01L29/423H01L29/45
CPCH01L29/41725H01L29/42316H01L29/452H01L29/66462H01L29/778
Inventor 莫炯炯王志宇陈华刘家瑞
Owner ZHEJIANG UNIV
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