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Oxide-based electronic synapse device and array thereof

An oxide-based, electronic synapse technology, applied in the direction of electrical solid devices, electrical components, semiconductor devices, etc., can solve the problems of high energy consumption, large device volatility, and difficulty in achieving large-scale integration, and achieve low energy consumption, ditch The channel conductance value is linear, which is conducive to the effect of large-scale integration

Pending Publication Date: 2020-06-12
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the current electronic synapse devices face many non-ideal factors based on the existing material systems: non-linearity of weight adjustment, asymmetry, large device fluctuations, high energy consumption, etc., such as Figure 1A shown in; at the same time limited by factors such as materials, such as MoO 3 When used as a channel layer or using ionic liquid as a gate dielectric layer, such as Figure 1B As shown, it is difficult to achieve large-scale integration

Method used

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  • Oxide-based electronic synapse device and array thereof
  • Oxide-based electronic synapse device and array thereof
  • Oxide-based electronic synapse device and array thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] Example 1 - oxide-based electronic synaptic device - planar top gate structure

[0038] In this example, if image 3 The oxide-based electronic synapse device with a planar top gate structure shown is prepared through the following steps, and the specific process flow is as follows: Figure 4 Shown:

[0039] Step 1: Oxidation to form SiO on the silicon wafer 2 layer, SiO 2 The thickness of the oxide layer is 100nm, and in other embodiments, the thickness of the oxide layer can be reduced or increased according to actual process conditions;

[0040] Step 2: Deposit source (Source) and drain (Drain) electrodes on the silicon oxide, the thickness of the source (Source) and drain (Drain) electrodes is 50nm. The source (Source) and drain (Drain) electrode materials are Pt electrodes; in other embodiments, the source (Source) and drain (Drain) electrode materials include but are not limited to the above materials, and other conductive materials can also be used;

[0041] S...

Embodiment 2

[0045] Example 2 - Oxide-based Electronic Synapse Device - Planar Bottom Gate Structure

[0046] In this example, if Figure 7 The oxide-based electronic synapse device with a planar bottom gate structure shown is prepared through the following steps, and the specific process is as follows: Figure 8 Shown:

[0047] Step 1: Oxidation to form SiO on the silicon wafer 2 layer, SiO 2 The thickness of the oxide layer is 100nm, and in other embodiments, the thickness of the oxide layer can be reduced or increased according to actual process conditions;

[0048] Step 2: Deposit the gate (Gate) electrode on the silicon oxide, the thickness of the gate (Gate) electrode is 100nm, the material of the gate (Gate) electrode is TiN electrode, in other embodiments, the gate electrode material includes but not limited to the above materials , other conductive materials can also be used;

[0049] Step 3: deposit an electrolyte layer on the gate (Gate) electrode, the thickness of the elec...

Embodiment 3

[0053] Example 3 - Oxide-based Electronic Synapse Device - Vertical Top Gate Structure

[0054] In this example, if Figure 9 The oxide-based electronic synapse device with a vertical top gate structure shown is prepared by the following steps, and the specific process flow is as follows: Figure 10 Shown:

[0055] Step 1: Oxidation to form SiO on the silicon wafer 2 layer, SiO 2 The thickness of the oxide layer is 100nm, and in other embodiments, the thickness of the oxide layer can be reduced or increased according to actual process conditions;

[0056] Step 2: deposit a drain electrode on silicon oxide, the thickness of the drain electrode is 50nm, and the drain electrode material is a TiN electrode. In other embodiments, the drain electrode material includes but is not limited to In addition to the above materials, other conductive materials can also be used;

[0057] Step 3: Deposit SiO on the drain electrode 2 The insulating material is used as an insulating isolat...

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Abstract

The invention discloses an oxide-based electronic synapse device and an array thereof. The device comprises a source electrode, a drain electrode and a gate electrode, a channel layer formed between the source electrode and the drain electrode and made of a solid oxide material; and an electrolyte layer, which is formed between the channel layer and the gate electrode as a gate medium, and which is an ion-conducting and electronically insulating solid electrolyte material. The device provided by the invention can well simulate a biological synaptic function, and has the advantages of polymorphism adjustability, high linearity, symmetry and the like, and an array integrated on a large scale can provide a device basis for constructing an artificial neural network.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an oxide-based electronic synapse device and an array thereof. Background technique [0002] The human brain can be considered as an efficient information storage and computing system with very low power consumption (~20W), and the biological synapse is considered as the core structural unit for energy-efficient information processing in the human brain. Facing the rapidly increasing amount of data and increasingly complex data types in human society, it is an important task in the field of information technology in the future to develop new electronic devices to simulate the function of biological synapses and build large-scale artificial neural networks to meet the current needs of high-energy-efficiency information processing. Direction of development. However, the current electronic synapse devices face many non-ideal factors based on the existing material syst...

Claims

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Application Information

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IPC IPC(8): H01L45/00H01L27/10
CPCH01L27/10H10N70/253H10N70/20H10N70/883H10N70/011
Inventor 尚大山李悦刘琦刘明刘宇
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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