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A kind of heterojunction bipolar transistor and its preparation method

A heterojunction bipolar and transistor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of high production cost, restrictions on SiGeHBT development and technology transformation, and long process development cycle, etc., to reduce Development and production costs, reduced collector width, and reduced parasitic effects

Active Publication Date: 2021-03-19
YANSHAN UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Although the performance of the device, especially its high-frequency characteristics, has been greatly improved, the long process development cycle and high production cost limit the development and technology transformation of SiGe HBT.

Method used

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  • A kind of heterojunction bipolar transistor and its preparation method
  • A kind of heterojunction bipolar transistor and its preparation method
  • A kind of heterojunction bipolar transistor and its preparation method

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Embodiment Construction

[0051] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0052] Such as figure 1 As shown, the heterojunction bipolar transistor of the present invention selects a P-type doped single-crystal Si substrate whose crystal orientation is (110); epitaxy a layer of N+ doped single-crystal Si layer on the substrate as a buried layer ; A layer of N-doped single crystal Si layer is epitaxially deposited on the surface of the buried layer as the collector area; three STI structures with a thickness of 400nm are formed in the collector area to realize the isolation of the collector and the base, and the collector N+ doping is performed on the right side of the region; ion implantation is performed on the N-doped collector region, and P+ doping is formed on both sides as an extrinsic base region; a layer with a thickness of 1-2 μm is deposited on the device surface SiO 2 layer to define the position of the active region; selectively ep...

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Abstract

The invention provides a heterojunction bipolar transistor and a preparation method thereof. Since the heterojunction bipolar transistor of the present invention has the same physical structure as the emitter region and the base region, the parasitic effect between the emitter region and the base region is effectively reduced, and the frequency characteristics of the device are improved; the emitter region has a width of 90 nanometers, effectively The intrinsic resistance of the base area is reduced; the embedded SiGe structure is adopted on both sides of the collector area, and the uniaxial strain is introduced at the same time as the biaxial strain, which will effectively reduce the carrier transmission time in the collector area. The width of the effective collector area is reduced, the capacitance of the collector junction is reduced, and the frequency characteristics of the device are further improved; appropriate selection of the thickness of the Si cap layer can effectively reduce the accumulation of carriers at the interface and improve the gain of the device; at the same time The preparation method of the bipolar transistor is fully compatible with the 90-nanometer CMOS process, effectively reducing the development and production costs of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a heterojunction bipolar transistor and a preparation method thereof. Background technique [0002] The CMOS process has entered the 7nm / 5nm node and is about to reach the end of the process development roadmap. In this context, the improvement of transistor performance mainly adopts strain engineering, high-K metal gate and transition from planar structure to three-dimensional structure. Starting from the 90nm process, the standard CMOS process mainly adopts the selective deposition method of SiGe layer in the source and drain regions, and introduces uniaxial stress in the channel region of the device. The introduction of stress can significantly increase the carrier mobility, thereby improving the performance of the device. However, in an actual circuit, as the size of the device decreases, the current driving capability of the device decreases, and ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/737H01L29/08H01L21/331
CPCH01L29/7375H01L29/7378H01L29/0817H01L29/0821H01L29/66242H01L29/7371H01L29/1004H01L29/41708
Inventor 周春宇常晓伟王冠宇耿欣蒋巍谭金波
Owner YANSHAN UNIV
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