Shift register, gate drive circuit, display panel and display device

Abstract

The invention discloses a shift register, a gate drive circuit, a display panel and a display device. The shift register comprises a second output module and a coupling module, and the two ends of thecoupling module are electrically connected with a third node and a second signal output end respectively. At the second stage, the potential of a fourth node is an enable potential, and the second output module transmits a high-potential signal of the first power supply signal input end to the second output end; at the third stage, the potential of the third node is an enable potential, and the second output module transmits a low-potential signal of the second power supply signal input end to the second output end, i.e., the signal of the second output end jumps from high to low, and at themoment, the low-potential signal of the second output end is coupled to the third node through the coupling effect of the coupling module, so that the potential of the third node is lower than that ofthe second stage, the low-potential signal of the second power supply signal input end has no transmission loss, the transistor controlled by the second signal output end can be completely turned off, and the leakage current loss is avoided.

Description

technical field [0001] Embodiments of the present invention relate to the field of display technology, and in particular, to a shift register, a gate drive circuit, a display panel, and a display device. Background technique [0002] With the development of display technology, while pursuing a higher resolution of the display device, the power consumption of the display device increases accordingly. In order to reduce power consumption of a display device, a frame rate may be reduced to drive pixels at a low speed during a certain period of time. For example, in a mobile terminal, the normal display mode executes a normal driving frequency based on 60 Hz or 120 Hz; in the standby mode, executes a driving frequency based on 1 Hz-5 Hz, thus reducing power consumption. [0003] Generally, in order to ensure display stability, a pixel driving circuit of a display device may be designed using a P-type metal oxide semiconductor field effect transistor (Positive Channel Metal Oxid...

AI Technical Summary

Problems solved by technology

However, due to the large leakage current of the PMOS formed by Low Temperature Poly-Silicon (LTPS) material, the data update cycle is longer when driving at a low frame rate. When there is a leakage current in the pixel, the display screen may appear Blinking, that is, it cannot be displayed normally

Therefore, some PMOS in the pixel driving circuit can be replaced by NMOS; A "down step", that is, the high level can only be converted to a low level after passing through an intermediate level, so that the high level cannot be effectively shifted, that is, the high potential signal and the low potential signal cannot be realized step by step without loss At the same time, the transistor controlled by the control terminal is not completely closed (that is, "cut off"), and there will still be leakage current, which will affect the display effect

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