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FPGA-based H.264 video encoding end, decoding end, transmission device and transmission method

A video encoding and video encoder technology, applied in the field of FPGA image encoding and decoding, to achieve the effect of reducing resource consumption, reducing read and write operations, and reducing peak transmission bandwidth requirements

Pending Publication Date: 2020-04-07
HUNAN JUNHAN INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Aiming at the problem of ultra-low delay that is difficult to achieve in the existing video codec system, the present invention provides an FPGA-based H.264 video encoding end, decoding end, transmission device and transmission method

Method used

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  • FPGA-based H.264 video encoding end, decoding end, transmission device and transmission method
  • FPGA-based H.264 video encoding end, decoding end, transmission device and transmission method

Examples

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Embodiment 1

[0031] refer to figure 1 , this embodiment provides an FPGA-based H.264 video encoding end-to-decoding end device for real-time data transmission, including an FPGA-based H.264 video encoding end and an FPGA-based H.264 video decoding end.

[0032] The FPGA-based H.264 video coding end includes:

[0033] Encoder main control module, using MB (Microblaze) processor soft core or ARM processor hard core in FPGA to initialize H.264 video encoder, including configuring video size, encoding compression rate and other parameters, and controlling H.264 Video encoder for encoding.

[0034] The H.264 video encoder encodes the video data under the control of the main control module of the encoding end, and every time 128 bytes of encoded data is generated, it is sent to the AXI-MM to AXI-S module in real time.

[0035] Encoder DDR module, which writes / reads the read and write data of the H.264 video encoder to / from the encoder DDR.

[0036] The AXI-MM to AXI-S module converts the enco...

Embodiment 2

[0045] This embodiment provides a real-time data transmission method from an FPGA-based H.264 video encoding end to a decoding end, including:

[0046]The H.264 video encoder at the H.264 video encoding end receives the video data and starts encoding. Every time 128 bytes of encoded data are generated, it is sent to the AXI-MM to AXI-S module in real time, and the encoding is performed through the AXI-MM to AXI-S module. The data is sent to the UDP Ethernet sending module after interface and bit width conversion, and the UDP Ethernet sending module starts sending every 128 bytes of data.

[0047] The UDP Ethernet receiving module of the H.264 video decoding end receives the compressed code stream data packet and transmits it to the AXI-S to AXI-MM module for interface and bit width conversion, and then caches it in the RAM of the AXI-S to AXI-MM module. After the AXI-S to AXI-MM module detects the data frame header, it delays 3ms and sends a decoding start interrupt to the mai...

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Abstract

The invention provides an FPGA-based H.264 video coding end, an H.264 video decoding end, a transmission device and a transmission method. The method comprises steps that H.264 video coding end videodata is sent; the H.264 video encoder receives the video data and starts encoding; each time 128-byte coded data is generated, the 128-byte coded data is sent to the AXI-MM-to-AXI-S module in real time, the AXI-MM-to-AXI-S module processes the coded data and then sends the coded data to the UDP Ethernet sending module, and the UDP Ethernet sending module starts sending every 128-byte data; after receiving the compressed code stream data packet, a UDP Ethernet receiving module of the H.264 video decoding end transmits the compressed code stream data packet to an RAM in an AXI-S-to-AXI-MM modulefor caching; after the AXI-S to AXI-MM module detects a data frame header, the AXI-S to AXI-MM module delays for 3ms and sends a decoding start interrupt to the decoding end main control module; andthe decoding end main control module controls the H.264 video decoder to start decoding, and the H.264 video decoder reads data from the RAM in the AXI-S-to-AXI-MM conversion module and decodes and outputs a video. The overall delay of a coding and decoding system is remarkably reduced, and the method is very suitable for low-bandwidth transmission modes such as wireless image transmission.

Description

technical field [0001] The invention relates to the technical field of FPGA image encoding and decoding, in particular to an encoding end, a decoding end, a transmission device and a transmission method that can be used for ultra-low delay transmission of real-time images. Background technique [0002] With the continuous development of video technology, users have higher and higher requirements for video compression coding, low-latency codec and transmission, especially for video transmission systems that require real-time control, the overall delay is generally lower than 100ms, and the lower the delay It will bring better handling experience. At present, the codec processor based on ARM core is widely used, and its functions are relatively complete, but it is not optimized for low-latency applications. The delay is generally 100-300ms, and it is widely used in cameras, sports cameras, video recorders, etc. that are not sensitive to delay. product. [0003] Due to the po...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/42H04N19/44H04N19/146
CPCH04N19/146H04N19/42H04N19/44
Inventor 彭骁寒焦斌
Owner HUNAN JUNHAN INFORMATION TECH CO LTD
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